TY - GEN
T1 - A Survey of Graph Neural Networks for Electronic Design Automation
AU - Lopera, Daniela Sanchez
AU - Servadei, Lorenzo
AU - Kiprit, Gamze Naz
AU - Hazra, Souvik
AU - Wille, Robert
AU - Ecker, Wolfgang
N1 - Publisher Copyright:
© 2021 IEEE.
PY - 2021/8/30
Y1 - 2021/8/30
N2 - Driven by Moore's law, the chip design complexity is steadily increasing. Electronic Design Automation (EDA) has been able to cope with the challenging very large-scale integration process, assuring scalability, reliability, and proper time-to-market. However, EDA approaches are time and resource-demanding, and they often do not guarantee optimal solutions. To alleviate these, Machine Learning (ML) has been incorporated into many stages of the design flow, such as in placement and routing. Many solutions employ Euclidean data and ML techniques without considering that many EDA objects are represented naturally as graphs. The trending Graph Neural Networks are an opportunity to solve EDA problems directly using graph structures for circuits, intermediate RTLs, and netlists. In this paper, we present a comprehensive review of the existing works linking the EDA flow for chip design and Graph Neural Networks.
AB - Driven by Moore's law, the chip design complexity is steadily increasing. Electronic Design Automation (EDA) has been able to cope with the challenging very large-scale integration process, assuring scalability, reliability, and proper time-to-market. However, EDA approaches are time and resource-demanding, and they often do not guarantee optimal solutions. To alleviate these, Machine Learning (ML) has been incorporated into many stages of the design flow, such as in placement and routing. Many solutions employ Euclidean data and ML techniques without considering that many EDA objects are represented naturally as graphs. The trending Graph Neural Networks are an opportunity to solve EDA problems directly using graph structures for circuits, intermediate RTLs, and netlists. In this paper, we present a comprehensive review of the existing works linking the EDA flow for chip design and Graph Neural Networks.
KW - Electronic Design Automation
KW - Graph Neural Networks
KW - Machine Learning
KW - Register-Transfer Level
KW - Very Large-scale Integration
UR - http://www.scopus.com/inward/record.url?scp=85115728472&partnerID=8YFLogxK
U2 - 10.1109/MLCAD52597.2021.9531070
DO - 10.1109/MLCAD52597.2021.9531070
M3 - Conference contribution
AN - SCOPUS:85115728472
T3 - 2021 ACM/IEEE 3rd Workshop on Machine Learning for CAD, MLCAD 2021
BT - 2021 ACM/IEEE 3rd Workshop on Machine Learning for CAD, MLCAD 2021
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 3rd ACM/IEEE Workshop on Machine Learning for CAD, MLCAD 2021
Y2 - 30 August 2021 through 3 September 2021
ER -