A Survey of Graph Neural Networks for Electronic Design Automation

Daniela Sanchez Lopera, Lorenzo Servadei, Gamze Naz Kiprit, Souvik Hazra, Robert Wille, Wolfgang Ecker

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

33 Scopus citations

Abstract

Driven by Moore's law, the chip design complexity is steadily increasing. Electronic Design Automation (EDA) has been able to cope with the challenging very large-scale integration process, assuring scalability, reliability, and proper time-to-market. However, EDA approaches are time and resource-demanding, and they often do not guarantee optimal solutions. To alleviate these, Machine Learning (ML) has been incorporated into many stages of the design flow, such as in placement and routing. Many solutions employ Euclidean data and ML techniques without considering that many EDA objects are represented naturally as graphs. The trending Graph Neural Networks are an opportunity to solve EDA problems directly using graph structures for circuits, intermediate RTLs, and netlists. In this paper, we present a comprehensive review of the existing works linking the EDA flow for chip design and Graph Neural Networks.

Original languageEnglish
Title of host publication2021 ACM/IEEE 3rd Workshop on Machine Learning for CAD, MLCAD 2021
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781665431668
DOIs
StatePublished - 30 Aug 2021
Externally publishedYes
Event3rd ACM/IEEE Workshop on Machine Learning for CAD, MLCAD 2021 - Raleigh, United States
Duration: 30 Aug 20213 Sep 2021

Publication series

Name2021 ACM/IEEE 3rd Workshop on Machine Learning for CAD, MLCAD 2021

Conference

Conference3rd ACM/IEEE Workshop on Machine Learning for CAD, MLCAD 2021
Country/TerritoryUnited States
CityRaleigh
Period30/08/213/09/21

Keywords

  • Electronic Design Automation
  • Graph Neural Networks
  • Machine Learning
  • Register-Transfer Level
  • Very Large-scale Integration

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