TY - GEN
T1 - A soft-core processor array for relational operators
AU - Polig, Raphael
AU - Giefers, Heiner
AU - Stechele, Walter
N1 - Publisher Copyright:
© 2015 IEEE.
PY - 2015/9/8
Y1 - 2015/9/8
N2 - Despite the performance and power efficiency gains achieved by FPGAs for text analytics queries, analysis shows a low utilization of the custom hardware operator modules. Furthermore the long synthesis times limit the accelerator's use in enterprise systems to static queries. To overcome these limitations we propose the use of an overlay architecture to share area resources among multiple operators and reduce compilation times. In this paper we present a novel soft-core architecture tailored to efficiently perform relational operations of text analytics queries on multiple virtual streams. It combines the ability to perform efficient streaming based operations while adding the flexibility of an instruction programmable core. It is used as a processing element in an array of cores to execute large query graphs and has access to shared co-processors to perform string-and context-based operations. We evaluate the core architecture in terms of area and performance compared to the custom hardware modules, and show how a minimum number of cores can be calculated to avoid stalling the document processing.
AB - Despite the performance and power efficiency gains achieved by FPGAs for text analytics queries, analysis shows a low utilization of the custom hardware operator modules. Furthermore the long synthesis times limit the accelerator's use in enterprise systems to static queries. To overcome these limitations we propose the use of an overlay architecture to share area resources among multiple operators and reduce compilation times. In this paper we present a novel soft-core architecture tailored to efficiently perform relational operations of text analytics queries on multiple virtual streams. It combines the ability to perform efficient streaming based operations while adding the flexibility of an instruction programmable core. It is used as a processing element in an array of cores to execute large query graphs and has access to shared co-processors to perform string-and context-based operations. We evaluate the core architecture in terms of area and performance compared to the custom hardware modules, and show how a minimum number of cores can be calculated to avoid stalling the document processing.
UR - http://www.scopus.com/inward/record.url?scp=84955602353&partnerID=8YFLogxK
U2 - 10.1109/ASAP.2015.7245699
DO - 10.1109/ASAP.2015.7245699
M3 - Conference contribution
AN - SCOPUS:84955602353
T3 - Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors
SP - 17
EP - 24
BT - Proceedings of the ASAP 2015 - 2015 IEEE 26th International Conference on Application-Specific Systems, Architectures and Processors
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 26th IEEE International Conference on Application-Specific Systems, Architectures and Processors, ASAP 2015
Y2 - 27 July 2015 through 29 July 2015
ER -