A Simulation Study of NBTI Impact on 14-nm Node FinFET Technology for Logic Applications: Device Degradation to Circuit-Level Interaction

Subrat Mishra; Hussam Amrouch; Jerin Joe; Chetan K. Dabhi; Karansingh Thakor; Yogesh S. Chauhan; Jorg Henkel; Souvik Mahapatra

doi:10.1109/TED.2018.2875813

A Simulation Study of NBTI Impact on 14-nm Node FinFET Technology for Logic Applications: Device Degradation to Circuit-Level Interaction

Subrat Mishra, Hussam Amrouch, Jerin Joe, Chetan K. Dabhi, Karansingh Thakor, Yogesh S. Chauhan, Jorg Henkel, Souvik Mahapatra

Research output: Contribution to journal › Article › peer-review

52 Scopus citations

Abstract

A comprehensive simulation flow is demonstrated to assess the negative-bias temperature instability (NBTI) impact on the performance and power of digital logic circuits based on the 14-nm node FinFET technology. Fully calibrated technology computer-aided design simulations are used to determine the preaged and postaged device characteristics; the results are used for calibrating the BSIM-CMG compact model. Standard cell libraries are characterized next, by only threshold voltage shift ( Δ V_T) and by both Δ V_T and subthreshold slope shift ( Δ SS). Various benchmark circuits are synthesized and analyzed, and their timing degradation is compared to ring oscillator results. The consequence of ignoring Δ SS on OFF current and static power ( P_static ) is estimated.

Original language	English
Article number	8510876
Pages (from-to)	271-278
Number of pages	8
Journal	IEEE Transactions on Electron Devices
Volume	66
Issue number	1
DOIs	https://doi.org/10.1109/TED.2018.2875813
State	Published - Jan 2019
Externally published	Yes

Keywords

BSIM-CMG
FinFET
SPICE
circuit simulation
compact model
mixed-mode simulation
negative-bias temperature instability (NBTI)
ring oscillator (RO)
standard cells
static power
subthreshold slope degradation

Access to Document

10.1109/TED.2018.2875813

Cite this

@article{08266c9e466e49dfab8af0f774de522d,

title = "A Simulation Study of NBTI Impact on 14-nm Node FinFET Technology for Logic Applications: Device Degradation to Circuit-Level Interaction",

abstract = "A comprehensive simulation flow is demonstrated to assess the negative-bias temperature instability (NBTI) impact on the performance and power of digital logic circuits based on the 14-nm node FinFET technology. Fully calibrated technology computer-aided design simulations are used to determine the preaged and postaged device characteristics; the results are used for calibrating the BSIM-CMG compact model. Standard cell libraries are characterized next, by only threshold voltage shift ( Δ VT) and by both Δ VT and subthreshold slope shift ( Δ SS). Various benchmark circuits are synthesized and analyzed, and their timing degradation is compared to ring oscillator results. The consequence of ignoring Δ SS on OFF current and static power ( Pstatic ) is estimated.",

keywords = "BSIM-CMG, FinFET, SPICE, circuit simulation, compact model, mixed-mode simulation, negative-bias temperature instability (NBTI), ring oscillator (RO), standard cells, static power, subthreshold slope degradation",

author = "Subrat Mishra and Hussam Amrouch and Jerin Joe and Dabhi, {Chetan K.} and Karansingh Thakor and Chauhan, {Yogesh S.} and Jorg Henkel and Souvik Mahapatra",

note = "Publisher Copyright: {\textcopyright} 1963-2012 IEEE.",

year = "2019",

month = jan,

doi = "10.1109/TED.2018.2875813",

language = "English",

volume = "66",

pages = "271--278",

journal = "IEEE Transactions on Electron Devices",

issn = "0018-9383",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "1",

}

TY - JOUR

T1 - A Simulation Study of NBTI Impact on 14-nm Node FinFET Technology for Logic Applications

T2 - Device Degradation to Circuit-Level Interaction

AU - Mishra, Subrat

AU - Amrouch, Hussam

AU - Joe, Jerin

AU - Dabhi, Chetan K.

AU - Thakor, Karansingh

AU - Chauhan, Yogesh S.

AU - Henkel, Jorg

AU - Mahapatra, Souvik

PY - 2019/1

Y1 - 2019/1

N2 - A comprehensive simulation flow is demonstrated to assess the negative-bias temperature instability (NBTI) impact on the performance and power of digital logic circuits based on the 14-nm node FinFET technology. Fully calibrated technology computer-aided design simulations are used to determine the preaged and postaged device characteristics; the results are used for calibrating the BSIM-CMG compact model. Standard cell libraries are characterized next, by only threshold voltage shift ( Δ VT) and by both Δ VT and subthreshold slope shift ( Δ SS). Various benchmark circuits are synthesized and analyzed, and their timing degradation is compared to ring oscillator results. The consequence of ignoring Δ SS on OFF current and static power ( Pstatic ) is estimated.

AB - A comprehensive simulation flow is demonstrated to assess the negative-bias temperature instability (NBTI) impact on the performance and power of digital logic circuits based on the 14-nm node FinFET technology. Fully calibrated technology computer-aided design simulations are used to determine the preaged and postaged device characteristics; the results are used for calibrating the BSIM-CMG compact model. Standard cell libraries are characterized next, by only threshold voltage shift ( Δ VT) and by both Δ VT and subthreshold slope shift ( Δ SS). Various benchmark circuits are synthesized and analyzed, and their timing degradation is compared to ring oscillator results. The consequence of ignoring Δ SS on OFF current and static power ( Pstatic ) is estimated.

KW - BSIM-CMG

KW - FinFET

KW - SPICE

KW - circuit simulation

KW - compact model

KW - mixed-mode simulation

KW - negative-bias temperature instability (NBTI)

KW - ring oscillator (RO)

KW - standard cells

KW - static power

KW - subthreshold slope degradation

UR - http://www.scopus.com/inward/record.url?scp=85055717822&partnerID=8YFLogxK

U2 - 10.1109/TED.2018.2875813

DO - 10.1109/TED.2018.2875813

M3 - Article

AN - SCOPUS:85055717822

SN - 0018-9383

VL - 66

SP - 271

EP - 278

JO - IEEE Transactions on Electron Devices

JF - IEEE Transactions on Electron Devices

IS - 1

M1 - 8510876

ER -

A Simulation Study of NBTI Impact on 14-nm Node FinFET Technology for Logic Applications: Device Degradation to Circuit-Level Interaction

Abstract

Keywords

Access to Document

Other files and links

Fingerprint

Cite this