TY - JOUR
T1 - A processing path dispatcher in network processor MPSoCs
AU - Ohlendorf, Rainer
AU - Meitinger, Michael
AU - Wild, Thomas
AU - Herkersdorf, Andreas
N1 - Funding Information:
Manuscript received October 25, 2007; revised June 12, 2008. Current version published September 19, 2008. This work was supported in part by the German Research Foundation (DFG). R. Ohlendorf is with the Technische Universität München, Institute for Integrated Systems, 80290 Munich, Germany (e-mail: [email protected]). M. Meitinger, T. Wild, and A. Herkersdorf are with the Technische Univer-sität München, Institute for Integrated Systems, 80290 Munich, Germany. Digital Object Identifier 10.1109/TVLSI.2008.2002048 Fig. 1. FlexPath NP with three DP-CPUs, one CP-CPU, and a Hardware Accelerator.
PY - 2008/10
Y1 - 2008/10
N2 - Multi-field packet classification problems discussed in the literature are typically constrained to the Internet five-tuple and primarily address the problem of network quality-of-service (QoS) support and access control. In this paper, we present a solution for a classification problem that is used for optimized packet assignment to different data paths within a network processor system-on-chip (SoC). In contrast to the five-tuple-based rules discussed in the prior art, our problem has rules that consider a larger set of fields from the packet header. However, for each individual rule a different sub-set of fields is relevant and the number of rules is smaller. Based on a specification of the usage case for our classifier we derive heterogeneous decision graph algorithm (HDGA), a heuristic approach to construct a decision tree classifier that integrates external lookup results for certain types of rules. We evaluate various parameters for optimizing the proposed decision tree and present simulation results to show the scalability of HDGA for typical problem sizes. This paper is concluded with the results of an implementation on our field-programmable gate-array (FPGA)-based prototyping platform.
AB - Multi-field packet classification problems discussed in the literature are typically constrained to the Internet five-tuple and primarily address the problem of network quality-of-service (QoS) support and access control. In this paper, we present a solution for a classification problem that is used for optimized packet assignment to different data paths within a network processor system-on-chip (SoC). In contrast to the five-tuple-based rules discussed in the prior art, our problem has rules that consider a larger set of fields from the packet header. However, for each individual rule a different sub-set of fields is relevant and the number of rules is smaller. Based on a specification of the usage case for our classifier we derive heterogeneous decision graph algorithm (HDGA), a heuristic approach to construct a decision tree classifier that integrates external lookup results for certain types of rules. We evaluate various parameters for optimizing the proposed decision tree and present simulation results to show the scalability of HDGA for typical problem sizes. This paper is concluded with the results of an implementation on our field-programmable gate-array (FPGA)-based prototyping platform.
KW - Communication systems
KW - Computer networks
KW - Network processors
KW - Packet classification
UR - http://www.scopus.com/inward/record.url?scp=52649114309&partnerID=8YFLogxK
U2 - 10.1109/TVLSI.2008.2002048
DO - 10.1109/TVLSI.2008.2002048
M3 - Article
AN - SCOPUS:52649114309
SN - 1063-8210
VL - 16
SP - 1335
EP - 1345
JO - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IS - 10
M1 - 4629345
ER -