A power efficient register file architecture using master latch sharing

M. Wróblewski, M. Mueller, A. Wortmann, S. Simon, W. Pieper, J. A. Nossek

Research output: Contribution to journalConference articlepeer-review

2 Scopus citations

Abstract

This paper introduces a method of reducing area and power consumption of a synthesizable register file by using a single master latch shared by a number of slaves. It investigates potential timing problems and discusses possible solutions. Presented simulation results show that, depending on the size of the register file, reduction of power consumption of more than 50% is achievable.

Original languageEnglish
Pages (from-to)V393-V396
JournalProceedings - IEEE International Symposium on Circuits and Systems
Volume5
StatePublished - 2003
EventProceedings of the 2003 IEEE International Symposium on Circuits and Systems - Bangkok, Thailand
Duration: 25 May 200328 May 2003

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