Abstract
This paper introduces a method of reducing area and power consumption of a synthesizable register file by using a single master latch shared by a number of slaves. It investigates potential timing problems and discusses possible solutions. Presented simulation results show that, depending on the size of the register file, reduction of power consumption of more than 50% is achievable.
Original language | English |
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Pages (from-to) | V393-V396 |
Journal | Proceedings - IEEE International Symposium on Circuits and Systems |
Volume | 5 |
State | Published - 2003 |
Event | Proceedings of the 2003 IEEE International Symposium on Circuits and Systems - Bangkok, Thailand Duration: 25 May 2003 → 28 May 2003 |