TY - GEN
T1 - A novel approach for nearest neighbor realization of 2d quantum circuits
AU - Bhattacharjee, Anirban
AU - Bandyopadhyay, Chandan
AU - Wille, Robert
AU - Drechsler, Rolf
AU - Rahaman, Hafizur
N1 - Publisher Copyright:
© 2018 IEEE.
PY - 2018/8/7
Y1 - 2018/8/7
N2 - Since decades, quantum computing has received tremendous attention among the researchers due to its dominance over classical computing. But simultaneously it has faced some design challenges and implementation constraints in this long run. One such constraint to build quantum circuits is to satisfy the so-called Nearest Neighbor (NN) property in the implemented circuits. Using SWAP gates, this constraint can be satisfied. But this leads to another design issue, namely how to determine such NN designs with a minimum use of SWAP gates. In way to further explore this area, in this work, we propose a heuristic approach for efficient NN complaint representation of quantum circuits in 2D space. The developed technique is segmented in three stages-qubit selection, qubit placement and SWAP gate insertion. The stated approach has been tested over a wide spectrum of benchmarks and reductions in cost parameters are observed. Improvement of more than 17%, 3% over 2D designs and 35%, 22% over 1D designs on SWAP count and quantum cost can be reported, respectively.
AB - Since decades, quantum computing has received tremendous attention among the researchers due to its dominance over classical computing. But simultaneously it has faced some design challenges and implementation constraints in this long run. One such constraint to build quantum circuits is to satisfy the so-called Nearest Neighbor (NN) property in the implemented circuits. Using SWAP gates, this constraint can be satisfied. But this leads to another design issue, namely how to determine such NN designs with a minimum use of SWAP gates. In way to further explore this area, in this work, we propose a heuristic approach for efficient NN complaint representation of quantum circuits in 2D space. The developed technique is segmented in three stages-qubit selection, qubit placement and SWAP gate insertion. The stated approach has been tested over a wide spectrum of benchmarks and reductions in cost parameters are observed. Improvement of more than 17%, 3% over 2D designs and 35%, 22% over 1D designs on SWAP count and quantum cost can be reported, respectively.
KW - Nearest Neighbour
KW - Quantum Circuit
KW - Quantum Cost
KW - Quantum gate
KW - SWAP gate
UR - http://www.scopus.com/inward/record.url?scp=85052158145&partnerID=8YFLogxK
U2 - 10.1109/ISVLSI.2018.00063
DO - 10.1109/ISVLSI.2018.00063
M3 - Conference contribution
AN - SCOPUS:85052158145
SN - 9781538670996
T3 - Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI
SP - 305
EP - 310
BT - Proceedings - 2018 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2018
PB - IEEE Computer Society
T2 - 17th IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2018
Y2 - 9 July 2018 through 11 July 2018
ER -