TY - GEN
T1 - A multi-platform controller allowing for maximum dynamic partial reconfiguration throughput
AU - Claus, C.
AU - Zhang, B.
AU - Stechele, W.
AU - Braun, L.
AU - Hübner, M.
AU - Becker, J.
PY - 2008
Y1 - 2008
N2 - Dynamic and Partial Reconfiguration (DPR) is a special feature offered by Xilinx Field Programmable Gate Arrays (FPGAs), giving the designer the ability to reconfigure a certain portion of the FPGA during run-time without influencing the other parts. This feature allows the hardware to be adaptable to any potential situation. For some applications, such as video-based driver assistance [1], the time needed to exchange a certain portion of the device might be critical. This paper addresses problems, limitations and results of on-chip reconfiguration that enable the user to decide whether DPR is suitable for a certain design prior to its implementation. A method is therefore introduced to calculate the expected reconfiguration throughput and latency. In addition, an IP core is presented that enables fast on-chip DPR close to the maximum achievable speed. Compared to an alternative state-of-the art realization, an increase in speed by a factor of 58 can be obtained.
AB - Dynamic and Partial Reconfiguration (DPR) is a special feature offered by Xilinx Field Programmable Gate Arrays (FPGAs), giving the designer the ability to reconfigure a certain portion of the FPGA during run-time without influencing the other parts. This feature allows the hardware to be adaptable to any potential situation. For some applications, such as video-based driver assistance [1], the time needed to exchange a certain portion of the device might be critical. This paper addresses problems, limitations and results of on-chip reconfiguration that enable the user to decide whether DPR is suitable for a certain design prior to its implementation. A method is therefore introduced to calculate the expected reconfiguration throughput and latency. In addition, an IP core is presented that enables fast on-chip DPR close to the maximum achievable speed. Compared to an alternative state-of-the art realization, an increase in speed by a factor of 58 can be obtained.
UR - http://www.scopus.com/inward/record.url?scp=54949092869&partnerID=8YFLogxK
U2 - 10.1109/FPL.2008.4630002
DO - 10.1109/FPL.2008.4630002
M3 - Conference contribution
AN - SCOPUS:54949092869
SN - 9781424419616
T3 - Proceedings - 2008 International Conference on Field Programmable Logic and Applications, FPL
SP - 535
EP - 538
BT - Proceedings - 2008 International Conference on Field Programmable Logic and Applications, FPL
T2 - 2008 International Conference on Field Programmable Logic and Applications, FPL
Y2 - 8 September 2008 through 10 September 2008
ER -