A Modular and Distributed Setup for Power and Performance Analysis of Multi-Processor System-on-Chip at Electronic System Level

Muhammad Mudussir Ayub; Franz Kreupl

doi:10.1109/IPCCC50635.2020.9391516

A Modular and Distributed Setup for Power and Performance Analysis of Multi-Processor System-on-Chip at Electronic System Level

Muhammad Mudussir Ayub, Franz Kreupl

Associate Professorship of Hybrid Electronic Systems

Technical University of Munich

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

1 Scopus citations

Abstract

5G brings innovation challenges for the spectra of computing and connectivity technology. Cellular modems, in particular, have to support various services and applications requiring low to high data rates. Therefore, the co-optimization of power and performance for architecture along circuit design is inevitable. In order to meet this challenge, this work presents a modular and distributed setup. It first separates functionality from architecture, and second, the way a power database is attached and integrated makes it practical. A simple use-case presented for the network processor demonstrates the effectiveness of the setup/methodology.

Original language	English
Title of host publication	2020 IEEE 39th International Performance Computing and Communications Conference, IPCCC 2020
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781728198293
DOIs	https://doi.org/10.1109/IPCCC50635.2020.9391516
State	Published - 6 Nov 2020
Event	39th IEEE International Performance Computing and Communications Conference, IPCCC 2020 - Austin, United States Duration: 6 Nov 2020 → 8 Nov 2020

Publication series

Name	2020 IEEE 39th International Performance Computing and Communications Conference, IPCCC 2020

Conference

Conference	39th IEEE International Performance Computing and Communications Conference, IPCCC 2020
Country/Territory	United States
City	Austin
Period	6/11/20 → 8/11/20

Keywords

design space exploration
electronic system level
performance models
power modeling
task graphs

Access to Document

10.1109/IPCCC50635.2020.9391516

Cite this

Ayub, M. M., & Kreupl, F. (2020). A Modular and Distributed Setup for Power and Performance Analysis of Multi-Processor System-on-Chip at Electronic System Level. In 2020 IEEE 39th International Performance Computing and Communications Conference, IPCCC 2020 Article 9391516 (2020 IEEE 39th International Performance Computing and Communications Conference, IPCCC 2020). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/IPCCC50635.2020.9391516

Ayub, Muhammad Mudussir ; Kreupl, Franz. / A Modular and Distributed Setup for Power and Performance Analysis of Multi-Processor System-on-Chip at Electronic System Level. 2020 IEEE 39th International Performance Computing and Communications Conference, IPCCC 2020. Institute of Electrical and Electronics Engineers Inc., 2020. (2020 IEEE 39th International Performance Computing and Communications Conference, IPCCC 2020).

@inproceedings{060ad7c75f834f49ad8807f3a046850a,

title = "A Modular and Distributed Setup for Power and Performance Analysis of Multi-Processor System-on-Chip at Electronic System Level",

abstract = "5G brings innovation challenges for the spectra of computing and connectivity technology. Cellular modems, in particular, have to support various services and applications requiring low to high data rates. Therefore, the co-optimization of power and performance for architecture along circuit design is inevitable. In order to meet this challenge, this work presents a modular and distributed setup. It first separates functionality from architecture, and second, the way a power database is attached and integrated makes it practical. A simple use-case presented for the network processor demonstrates the effectiveness of the setup/methodology.",

keywords = "design space exploration, electronic system level, performance models, power modeling, task graphs",

author = "Ayub, {Muhammad Mudussir} and Franz Kreupl",

note = "Publisher Copyright: {\textcopyright} 2020 IEEE.; 39th IEEE International Performance Computing and Communications Conference, IPCCC 2020 ; Conference date: 06-11-2020 Through 08-11-2020",

year = "2020",

month = nov,

day = "6",

doi = "10.1109/IPCCC50635.2020.9391516",

language = "English",

series = "2020 IEEE 39th International Performance Computing and Communications Conference, IPCCC 2020",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "2020 IEEE 39th International Performance Computing and Communications Conference, IPCCC 2020",

}

Ayub, MM & Kreupl, F 2020, A Modular and Distributed Setup for Power and Performance Analysis of Multi-Processor System-on-Chip at Electronic System Level. in 2020 IEEE 39th International Performance Computing and Communications Conference, IPCCC 2020., 9391516, 2020 IEEE 39th International Performance Computing and Communications Conference, IPCCC 2020, Institute of Electrical and Electronics Engineers Inc., 39th IEEE International Performance Computing and Communications Conference, IPCCC 2020, Austin, United States, 6/11/20. https://doi.org/10.1109/IPCCC50635.2020.9391516

A Modular and Distributed Setup for Power and Performance Analysis of Multi-Processor System-on-Chip at Electronic System Level. / Ayub, Muhammad Mudussir; Kreupl, Franz.
2020 IEEE 39th International Performance Computing and Communications Conference, IPCCC 2020. Institute of Electrical and Electronics Engineers Inc., 2020. 9391516 (2020 IEEE 39th International Performance Computing and Communications Conference, IPCCC 2020).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - A Modular and Distributed Setup for Power and Performance Analysis of Multi-Processor System-on-Chip at Electronic System Level

AU - Ayub, Muhammad Mudussir

AU - Kreupl, Franz

PY - 2020/11/6

Y1 - 2020/11/6

N2 - 5G brings innovation challenges for the spectra of computing and connectivity technology. Cellular modems, in particular, have to support various services and applications requiring low to high data rates. Therefore, the co-optimization of power and performance for architecture along circuit design is inevitable. In order to meet this challenge, this work presents a modular and distributed setup. It first separates functionality from architecture, and second, the way a power database is attached and integrated makes it practical. A simple use-case presented for the network processor demonstrates the effectiveness of the setup/methodology.

AB - 5G brings innovation challenges for the spectra of computing and connectivity technology. Cellular modems, in particular, have to support various services and applications requiring low to high data rates. Therefore, the co-optimization of power and performance for architecture along circuit design is inevitable. In order to meet this challenge, this work presents a modular and distributed setup. It first separates functionality from architecture, and second, the way a power database is attached and integrated makes it practical. A simple use-case presented for the network processor demonstrates the effectiveness of the setup/methodology.

KW - design space exploration

KW - electronic system level

KW - performance models

KW - power modeling

KW - task graphs

UR - http://www.scopus.com/inward/record.url?scp=85104383957&partnerID=8YFLogxK

U2 - 10.1109/IPCCC50635.2020.9391516

DO - 10.1109/IPCCC50635.2020.9391516

M3 - Conference contribution

AN - SCOPUS:85104383957

T3 - 2020 IEEE 39th International Performance Computing and Communications Conference, IPCCC 2020

BT - 2020 IEEE 39th International Performance Computing and Communications Conference, IPCCC 2020

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 39th IEEE International Performance Computing and Communications Conference, IPCCC 2020

Y2 - 6 November 2020 through 8 November 2020

ER -

Ayub MM, Kreupl F. A Modular and Distributed Setup for Power and Performance Analysis of Multi-Processor System-on-Chip at Electronic System Level. In 2020 IEEE 39th International Performance Computing and Communications Conference, IPCCC 2020. Institute of Electrical and Electronics Engineers Inc. 2020. 9391516. (2020 IEEE 39th International Performance Computing and Communications Conference, IPCCC 2020). doi: 10.1109/IPCCC50635.2020.9391516

A Modular and Distributed Setup for Power and Performance Analysis of Multi-Processor System-on-Chip at Electronic System Level

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