A Mixed-Signal Interface Circuit for Integration of Embedded 1T1R RRAM Arrays

Stefan Pechmann; Amelie Hagelauer

doi:10.1109/SOCC56010.2022.9908137

A Mixed-Signal Interface Circuit for Integration of Embedded 1T1R RRAM Arrays

Stefan Pechmann, Amelie Hagelauer

Chair of Micro- and Nanosystems Technology

Technical University of Munich

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

1 Scopus citations

Abstract

The system integration of Resistive Random Access Memory (RRAM) as embedded memory is a key issue to enable the usage of this emerging technology. The integration of the individual memory cells in CMOS circuits demands analog operations to realize forming, programming and reading of the individual RRAM cells. The presented circuit bridges this gap between technological research and system design with a circuit capable of these operations while offering a fully-digital interface to allow easy system integration. This enables the usage of RRAM technology as embedded memory without extensive analog knowledge on transistor level.The presented circuit was designed, simulated and layouted using IHP's MEMRES Module, but can be adapted to other RRAM technologies by changing just a few circuit parameters. Due to its flexibility, it can mitigate the technologies' intrinsic variability and offers a wide degree of adaptability for different application scenarios. The presented read concept is able to resolve four states with an overall resistance ratio of 3.7. The programming mode enables multi-level set and reset operations with fully-digital control and complete CMOS integration.

Original language	English
Title of host publication	Proceedings - 2022 IEEE 35th International System-on-Chip Conference, SOCC 2022
Editors	Sakir Sezer, Thomas Buchner, Jurgen Becker, Andrew Marshall, Fahad Siddiqui, Tanja Harbaum, Kieran McLaughlin
Publisher	IEEE Computer Society
ISBN (Electronic)	9781665459853
DOIs	https://doi.org/10.1109/SOCC56010.2022.9908137
State	Published - 2022
Event	35th IEEE International System-on-Chip Conference, SOCC 2022 - Belfast, Northern Ireland, United Kingdom Duration: 5 Sep 2022 → 8 Sep 2022

Publication series

Name	International System on Chip Conference
Volume	2022-September
ISSN (Print)	2164-1676
ISSN (Electronic)	2164-1706

Conference

Conference	35th IEEE International System-on-Chip Conference, SOCC 2022
Country/Territory	United Kingdom
City	Belfast, Northern Ireland
Period	5/09/22 → 8/09/22

Keywords

1T1R
Embedded Memory
Interface Circuit
Memory Integration
Mixed-Signal
RRAM

Access to Document

10.1109/SOCC56010.2022.9908137

Cite this

Pechmann, S., & Hagelauer, A. (2022). A Mixed-Signal Interface Circuit for Integration of Embedded 1T1R RRAM Arrays. In S. Sezer, T. Buchner, J. Becker, A. Marshall, F. Siddiqui, T. Harbaum, & K. McLaughlin (Eds.), Proceedings - 2022 IEEE 35th International System-on-Chip Conference, SOCC 2022 (International System on Chip Conference; Vol. 2022-September). IEEE Computer Society. https://doi.org/10.1109/SOCC56010.2022.9908137

Pechmann, Stefan ; Hagelauer, Amelie. / A Mixed-Signal Interface Circuit for Integration of Embedded 1T1R RRAM Arrays. Proceedings - 2022 IEEE 35th International System-on-Chip Conference, SOCC 2022. editor / Sakir Sezer ; Thomas Buchner ; Jurgen Becker ; Andrew Marshall ; Fahad Siddiqui ; Tanja Harbaum ; Kieran McLaughlin. IEEE Computer Society, 2022. (International System on Chip Conference).

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title = "A Mixed-Signal Interface Circuit for Integration of Embedded 1T1R RRAM Arrays",

abstract = "The system integration of Resistive Random Access Memory (RRAM) as embedded memory is a key issue to enable the usage of this emerging technology. The integration of the individual memory cells in CMOS circuits demands analog operations to realize forming, programming and reading of the individual RRAM cells. The presented circuit bridges this gap between technological research and system design with a circuit capable of these operations while offering a fully-digital interface to allow easy system integration. This enables the usage of RRAM technology as embedded memory without extensive analog knowledge on transistor level.The presented circuit was designed, simulated and layouted using IHP's MEMRES Module, but can be adapted to other RRAM technologies by changing just a few circuit parameters. Due to its flexibility, it can mitigate the technologies' intrinsic variability and offers a wide degree of adaptability for different application scenarios. The presented read concept is able to resolve four states with an overall resistance ratio of 3.7. The programming mode enables multi-level set and reset operations with fully-digital control and complete CMOS integration.",

keywords = "1T1R, Embedded Memory, Interface Circuit, Memory Integration, Mixed-Signal, RRAM",

author = "Stefan Pechmann and Amelie Hagelauer",

note = "Publisher Copyright: {\textcopyright} 2022 IEEE.; 35th IEEE International System-on-Chip Conference, SOCC 2022 ; Conference date: 05-09-2022 Through 08-09-2022",

year = "2022",

doi = "10.1109/SOCC56010.2022.9908137",

language = "English",

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Pechmann, S & Hagelauer, A 2022, A Mixed-Signal Interface Circuit for Integration of Embedded 1T1R RRAM Arrays. in S Sezer, T Buchner, J Becker, A Marshall, F Siddiqui, T Harbaum & K McLaughlin (eds), Proceedings - 2022 IEEE 35th International System-on-Chip Conference, SOCC 2022. International System on Chip Conference, vol. 2022-September, IEEE Computer Society, 35th IEEE International System-on-Chip Conference, SOCC 2022, Belfast, Northern Ireland, United Kingdom, 5/09/22. https://doi.org/10.1109/SOCC56010.2022.9908137

A Mixed-Signal Interface Circuit for Integration of Embedded 1T1R RRAM Arrays. / Pechmann, Stefan; Hagelauer, Amelie.
Proceedings - 2022 IEEE 35th International System-on-Chip Conference, SOCC 2022. ed. / Sakir Sezer; Thomas Buchner; Jurgen Becker; Andrew Marshall; Fahad Siddiqui; Tanja Harbaum; Kieran McLaughlin. IEEE Computer Society, 2022. (International System on Chip Conference; Vol. 2022-September).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Pechmann, Stefan

AU - Hagelauer, Amelie

PY - 2022

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N2 - The system integration of Resistive Random Access Memory (RRAM) as embedded memory is a key issue to enable the usage of this emerging technology. The integration of the individual memory cells in CMOS circuits demands analog operations to realize forming, programming and reading of the individual RRAM cells. The presented circuit bridges this gap between technological research and system design with a circuit capable of these operations while offering a fully-digital interface to allow easy system integration. This enables the usage of RRAM technology as embedded memory without extensive analog knowledge on transistor level.The presented circuit was designed, simulated and layouted using IHP's MEMRES Module, but can be adapted to other RRAM technologies by changing just a few circuit parameters. Due to its flexibility, it can mitigate the technologies' intrinsic variability and offers a wide degree of adaptability for different application scenarios. The presented read concept is able to resolve four states with an overall resistance ratio of 3.7. The programming mode enables multi-level set and reset operations with fully-digital control and complete CMOS integration.

AB - The system integration of Resistive Random Access Memory (RRAM) as embedded memory is a key issue to enable the usage of this emerging technology. The integration of the individual memory cells in CMOS circuits demands analog operations to realize forming, programming and reading of the individual RRAM cells. The presented circuit bridges this gap between technological research and system design with a circuit capable of these operations while offering a fully-digital interface to allow easy system integration. This enables the usage of RRAM technology as embedded memory without extensive analog knowledge on transistor level.The presented circuit was designed, simulated and layouted using IHP's MEMRES Module, but can be adapted to other RRAM technologies by changing just a few circuit parameters. Due to its flexibility, it can mitigate the technologies' intrinsic variability and offers a wide degree of adaptability for different application scenarios. The presented read concept is able to resolve four states with an overall resistance ratio of 3.7. The programming mode enables multi-level set and reset operations with fully-digital control and complete CMOS integration.

KW - 1T1R

KW - Embedded Memory

KW - Interface Circuit

KW - Memory Integration

KW - Mixed-Signal

KW - RRAM

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BT - Proceedings - 2022 IEEE 35th International System-on-Chip Conference, SOCC 2022

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A2 - Buchner, Thomas

A2 - Becker, Jurgen

A2 - Marshall, Andrew

A2 - Siddiqui, Fahad

A2 - Harbaum, Tanja

A2 - McLaughlin, Kieran

PB - IEEE Computer Society

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Y2 - 5 September 2022 through 8 September 2022

ER -

Pechmann S, Hagelauer A. A Mixed-Signal Interface Circuit for Integration of Embedded 1T1R RRAM Arrays. In Sezer S, Buchner T, Becker J, Marshall A, Siddiqui F, Harbaum T, McLaughlin K, editors, Proceedings - 2022 IEEE 35th International System-on-Chip Conference, SOCC 2022. IEEE Computer Society. 2022. (International System on Chip Conference). doi: 10.1109/SOCC56010.2022.9908137

A Mixed-Signal Interface Circuit for Integration of Embedded 1T1R RRAM Arrays

Abstract

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Keywords

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