A method for phase noise analysis of RF circuits

Dimo Martev, Sven Hampel, Ulf Schlichtmann

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations

Abstract

In this paper we present a method for analysis of phase noise in logic circuits. This method alLows the design and verification of phase noise critical circuits using a digital toolchain, significantly reducing the design time and effort compared to the traditional approach using analog tools such as SPICE simulation. It is based on a set of pre-characterized standard cells and the generated phase noise is estimated using a lookup table approach. Comparison of the estimation results with back-annotated analog simulations in 28 nm CMOS technology show that the error of the estimation is within 7.2% of the actual phase noise, and the runtime is reduced by three orders of magnitude.

Original languageEnglish
Title of host publicationGLSVLSI 2017 - Proceedings of the Great Lakes Symposium on VLSI 2017
PublisherAssociation for Computing Machinery
Pages227-231
Number of pages5
ISBN (Electronic)9781450349727
DOIs
StatePublished - 10 May 2017
Event27th Great Lakes Symposium on VLSI, GLSVLSI 2017 - Banff, Canada
Duration: 10 May 201712 May 2017

Publication series

NameProceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI
VolumePart F127756

Conference

Conference27th Great Lakes Symposium on VLSI, GLSVLSI 2017
Country/TerritoryCanada
CityBanff
Period10/05/1712/05/17

Keywords

  • Phase noise
  • Phase noise analysis
  • RF circuits

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