A long duration transient resilient pipeline scheme

Single event transients (SETs) in combinational logic remain an important topic in the reliability domain. SETs were traditionally relatively short in comparison to the clock period. The majority of the countermeasures utilizes this property. However, advances in technology scaling will reverse the ratio for complementary metal-oxide semiconductor devices. Investigations show that SETs may last up to multiple clock cycles in the future. So-called long duration transients (LDTs) corrupt almost all available countermeasures. This paper presents a new methodology to tackle LDTs. Dual modular redundancy (DMR) is used to detect any corruption of the application logic. A new micro-rollback scheme expands the DMR architecture with fault correction capabilities. The concept is also capable of handling single event upsets and timing violations. The correction penalty is two clock cycles. The approach was implemented and verified in a Viterbi decoder architecture. The scheme utilizes a newly designed History Cell. The History Cell introduces an area overhead of 97% and a power overhead of 110%, compared to a standard cell DFF.