A layered adaptive verification platform for simulation, test, and emulation

Martin Zambaldi; Wolfgang Ecker; Renate Henftling; Matthias Bauer

doi:10.1109/MDT.2004.73

A layered adaptive verification platform for simulation, test, and emulation

Martin Zambaldi
, Wolfgang Ecker
, Renate Henftling
, Matthias Bauer

Infineon Technologies AG

Research output: Contribution to journal › Article › peer-review

6 Scopus citations

Abstract

This Adaptive architecture for structuring testbenches accommodate various models of a design, from transaction to silicon. Moreover, the adapter based architecture supports the execution of design models of different sumulators (high level, RTL, gate level, and switch level), hardware emulators (the testbench runs entirely on the emulator), and even testers.

Original language	English
Pages (from-to)	464-471
Number of pages	8
Journal	IEEE Design and Test of Computers
Volume	21
Issue number	6
DOIs	https://doi.org/10.1109/MDT.2004.73
State	Published - Nov 2004
Externally published	Yes

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10.1109/MDT.2004.73

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title = "A layered adaptive verification platform for simulation, test, and emulation",

abstract = "This Adaptive architecture for structuring testbenches accommodate various models of a design, from transaction to silicon. Moreover, the adapter based architecture supports the execution of design models of different sumulators (high level, RTL, gate level, and switch level), hardware emulators (the testbench runs entirely on the emulator), and even testers.",

author = "Martin Zambaldi and Wolfgang Ecker and Renate Henftling and Matthias Bauer",

year = "2004",

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AU - Zambaldi, Martin

AU - Ecker, Wolfgang

AU - Henftling, Renate

AU - Bauer, Matthias

PY - 2004/11

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AB - This Adaptive architecture for structuring testbenches accommodate various models of a design, from transaction to silicon. Moreover, the adapter based architecture supports the execution of design models of different sumulators (high level, RTL, gate level, and switch level), hardware emulators (the testbench runs entirely on the emulator), and even testers.

UR - https://www.scopus.com/pages/publications/11244317294

U2 - 10.1109/MDT.2004.73

DO - 10.1109/MDT.2004.73

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JO - IEEE Design and Test of Computers

JF - IEEE Design and Test of Computers

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ER -

A layered adaptive verification platform for simulation, test, and emulation

Abstract

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