A hardware packet re-sequencer unit for network processors

Michael Meitinger, Rainer Ohlendorf, Thomas Wild, Andreas Herkersdorf

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

8 Scopus citations


Network Processors (NP) usually are designed as multi-processor systems with parallel packet processing. This parallelism may lead to flows with packets out-of-order when leaving the NP system. But packet reordering has a bad impact on network performance, especially when using the dominating TCP protocol. In this paper, we describe a Hardware Re-Sequencer Unit for Network Processors. Incoming packets will be tagged in the ingress path, preserving the packet order with flow granularity. An Aggregation Unit reorders the packet flows in the egress path if needed. In contrast to most other solutions the way of the packet through the NP system is dispensable, which enlarges design freedom in terms of e.g. load balancing. After explaining the general concept, a SystemC model is presented. Simulation results are used for dimensioning and a proof of concept with real traffic traces. General aspects concerning the implementation are discussed.

Original languageEnglish
Title of host publicationArchitecture of Computing Systems - ARCS 2008 - 21st International Conference, Proceedings
Number of pages13
StatePublished - 2008
Event21st International Conference on Architecture of Computing Systems, ARCS 2008 - Dresden, Germany
Duration: 25 Feb 200828 Feb 2008

Publication series

NameLecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Volume4934 LNCS
ISSN (Print)0302-9743
ISSN (Electronic)1611-3349


Conference21st International Conference on Architecture of Computing Systems, ARCS 2008


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