TY - GEN
T1 - A hardware packet re-sequencer unit for network processors
AU - Meitinger, Michael
AU - Ohlendorf, Rainer
AU - Wild, Thomas
AU - Herkersdorf, Andreas
PY - 2008
Y1 - 2008
N2 - Network Processors (NP) usually are designed as multi-processor systems with parallel packet processing. This parallelism may lead to flows with packets out-of-order when leaving the NP system. But packet reordering has a bad impact on network performance, especially when using the dominating TCP protocol. In this paper, we describe a Hardware Re-Sequencer Unit for Network Processors. Incoming packets will be tagged in the ingress path, preserving the packet order with flow granularity. An Aggregation Unit reorders the packet flows in the egress path if needed. In contrast to most other solutions the way of the packet through the NP system is dispensable, which enlarges design freedom in terms of e.g. load balancing. After explaining the general concept, a SystemC model is presented. Simulation results are used for dimensioning and a proof of concept with real traffic traces. General aspects concerning the implementation are discussed.
AB - Network Processors (NP) usually are designed as multi-processor systems with parallel packet processing. This parallelism may lead to flows with packets out-of-order when leaving the NP system. But packet reordering has a bad impact on network performance, especially when using the dominating TCP protocol. In this paper, we describe a Hardware Re-Sequencer Unit for Network Processors. Incoming packets will be tagged in the ingress path, preserving the packet order with flow granularity. An Aggregation Unit reorders the packet flows in the egress path if needed. In contrast to most other solutions the way of the packet through the NP system is dispensable, which enlarges design freedom in terms of e.g. load balancing. After explaining the general concept, a SystemC model is presented. Simulation results are used for dimensioning and a proof of concept with real traffic traces. General aspects concerning the implementation are discussed.
UR - http://www.scopus.com/inward/record.url?scp=49949084266&partnerID=8YFLogxK
U2 - 10.1007/978-3-540-78153-0_8
DO - 10.1007/978-3-540-78153-0_8
M3 - Conference contribution
AN - SCOPUS:49949084266
SN - 3540781528
SN - 9783540781523
T3 - Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
SP - 85
EP - 97
BT - Architecture of Computing Systems - ARCS 2008 - 21st International Conference, Proceedings
T2 - 21st International Conference on Architecture of Computing Systems, ARCS 2008
Y2 - 25 February 2008 through 28 February 2008
ER -