A hardware-based multi-objective thread mapper for tiled manycore architectures

Keyphrases

• Control Unit 100%
• Mapper 100%
• Many-core Architecture 100%
• Hardware Efficiency 100%
• Thread Mapping 75%
• Robin 50%
• Single-objective 50%
• Thread Scheduling 50%
• Physical Constraints 25%
• Latency 25%
• Load Balancing 25%
• Scheduler 25%
• Many-core Processor 25%
• Hardware Overhead 25%
• Multi-processor System-on-chip (MPSoC) 25%
• Power Budget 25%
• System Scheduling 25%
• Sensory Parameters 25%
• Operating System 25%
• Processor Core 25%
• Low Latency 25%
• FPGA Prototype 25%
• Objective Performance 25%
• Performance Optimization 25%
• ASIC Synthesis 25%
• Management Strategy 25%
• Performance Criteria 25%
• Load Performance 25%
• Mapping Policy 25%
• Temperature Limitation 25%
• Thermal Resilience 25%
• Hardware Thread 25%
• FPGA Synthesis 25%
• Power Resilience 25%
• Periodic Traffic 25%
• Bursty Traffic 25%
• Temperature Reliability 25%
• Low Overhead 25%

Computer Science

• Multiobjective 100%
• Control Unit 100%
• Computer Hardware 100%
• Single Objective 75%
• Thread Management 50%
• Field Programmable Gate Arrays 50%
• Load Balancing 25%
• Application Specific Integrated Circuit 25%
• Hardware Overhead 25%
• Clock Cycle 25%
• Performance Optimization 25%
• Hardware Thread 25%
• Processor Core 25%
• Physical Constraint 25%
• Performance Criterion 25%
• Operating System 25%