A flexible Segment Matching Processor for Motion and Illumination Estimation

This paper describes a flexible 100 Giga operations per second (GOPS) exhaustive search block matching VLSI to support evolving motion estimation (ME) algorithms as well as established video coding standards. The architecture is based on a 32×32 PE (processor element) array and a 10240 byte on-chip search area RAM and allows concurrent calculation of motion vectors for 32×32, 16×16, 8×8 and 4×4 blocks and subblock clusters for a +/-32 pel search range with 100% PE utilization. Arbitrarily shaped video objects introduced by the emerging MPEG-4 standard as well as advanced algorithms like variable blocksize ME and illumination-corrected ME of partial quadtrees are supported. The 0.35 μm CMOS VLSI has been designed using VHDL synthesis, resulting in a total chip size of slightly above 100 mm² at 100 Mhz clock (min.). The maximum throughput is 23668 32×32 blocks/second at +/-32 pel search range.