TY - GEN
T1 - A flexible PC-controlled analog/digital test set for CNNs
AU - Köhn, Immanuel
AU - Smith, Bernhard
AU - Harrer, Hubert
AU - Nossek, J. A.
N1 - Publisher Copyright:
© 1992 IEEE.
PY - 1992
Y1 - 1992
N2 - This paper describes a flexible test set that allows PC-controlled analog and digital measurements of a test object. The concept is modularly structured and enables an individual constellation depending on the testing object such as a CNN chip. Analog and digital signals can be transferred to and from the object. The communication to the PC is realized via a standard interface. For the PC, a test program language (TPL) has been developed, which is easy to handle and allows a flexible and completely automatic testing of a chip. The results of the measurement (e.g., dc characteristics) can be graphically visualized. For dynamic measurements the bottle neck consists in the data transfer to the PC and the processing of the testprogram interpreter. To overcome this problem special hardware modules have been developed, which allow a cyclic or linear output of analog and digital signals up to 10 MHz. Their core consists of a FIFO, which is preloaded before the processing. The output rate is controlled by a clock and different modules are synchronized via trigger signals.
AB - This paper describes a flexible test set that allows PC-controlled analog and digital measurements of a test object. The concept is modularly structured and enables an individual constellation depending on the testing object such as a CNN chip. Analog and digital signals can be transferred to and from the object. The communication to the PC is realized via a standard interface. For the PC, a test program language (TPL) has been developed, which is easy to handle and allows a flexible and completely automatic testing of a chip. The results of the measurement (e.g., dc characteristics) can be graphically visualized. For dynamic measurements the bottle neck consists in the data transfer to the PC and the processing of the testprogram interpreter. To overcome this problem special hardware modules have been developed, which allow a cyclic or linear output of analog and digital signals up to 10 MHz. Their core consists of a FIFO, which is preloaded before the processing. The output rate is controlled by a clock and different modules are synchronized via trigger signals.
UR - http://www.scopus.com/inward/record.url?scp=77957712599&partnerID=8YFLogxK
U2 - 10.1109/CNNA.1992.274364
DO - 10.1109/CNNA.1992.274364
M3 - Conference contribution
AN - SCOPUS:77957712599
T3 - Proceedings - 2nd International Workshop on Cellular Neural Networks and their Applications, CNNA 1992
SP - 228
EP - 233
BT - Proceedings - 2nd International Workshop on Cellular Neural Networks and their Applications, CNNA 1992
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2nd International Workshop on Cellular Neural Networks and their Applications, CNNA 1992
Y2 - 14 October 1992 through 16 October 1992
ER -