A Dynamic Charge-Transfer-Based Crossbar with Low Sensitivity to Parasitic Wire-Resistance

Compute-In-Memory (CIM) enables accelerating multiply-accumulate computations (MACs) by non von Neumann architecture analog crossbars. However, computation precision and power efficiency suffer from parasitic wire resistance and power-consuming data-converters with conventional voltage-mode crossbar. Increasing crossbar size to further enhance computation/power efficiency can only be achieved on the premise that those problems can be solved. This work proposes a charge-transfer-based crossbar, where the accumulation is performed by counting the transferred charges into capacitors. Thanks to the time-discrete property of the charge transfer and adaptive body-biasing (ABB) current generator, the entire proposed crossbar is almost fully dynamic and very insensitive to parasitic wire resistance without DAC/ADC needed. In addition, adaptive reference technique is applied to realize a self-adjustable operating range for quantitated neural network computations. The proposed crossbar prototype is designed with 22nm-FDSOI and post-simulated with a size of 128 times 128. A computation and power efficiency of 1024GOP/s and 78TOPS/w is achieved for computation with 4-bit inputs, 1-bit weight, and 4-bit output. Both computation-and power efficiency can be further enhanced by enlarging the crossbars' size without any significant loss of the computation precision.