TY - GEN
T1 - A Dynamic Charge-Transfer-Based Crossbar with Low Sensitivity to Parasitic Wire-Resistance
AU - Xu, Pengcheng
AU - Zhang, Lei
AU - Pscheidl, Ferdinand
AU - Borggreve, David
AU - Vanselow, Frank
AU - Brederlow, Ralf
N1 - Publisher Copyright:
© 2022 IEEE.
PY - 2022
Y1 - 2022
N2 - Compute-In-Memory (CIM) enables accelerating multiply-accumulate computations (MACs) by non von Neumann architecture analog crossbars. However, computation precision and power efficiency suffer from parasitic wire resistance and power-consuming data-converters with conventional voltage-mode crossbar. Increasing crossbar size to further enhance computation/power efficiency can only be achieved on the premise that those problems can be solved. This work proposes a charge-transfer-based crossbar, where the accumulation is performed by counting the transferred charges into capacitors. Thanks to the time-discrete property of the charge transfer and adaptive body-biasing (ABB) current generator, the entire proposed crossbar is almost fully dynamic and very insensitive to parasitic wire resistance without DAC/ADC needed. In addition, adaptive reference technique is applied to realize a self-adjustable operating range for quantitated neural network computations. The proposed crossbar prototype is designed with 22nm-FDSOI and post-simulated with a size of 128 times 128. A computation and power efficiency of 1024GOP/s and 78TOPS/w is achieved for computation with 4-bit inputs, 1-bit weight, and 4-bit output. Both computation-and power efficiency can be further enhanced by enlarging the crossbars' size without any significant loss of the computation precision.
AB - Compute-In-Memory (CIM) enables accelerating multiply-accumulate computations (MACs) by non von Neumann architecture analog crossbars. However, computation precision and power efficiency suffer from parasitic wire resistance and power-consuming data-converters with conventional voltage-mode crossbar. Increasing crossbar size to further enhance computation/power efficiency can only be achieved on the premise that those problems can be solved. This work proposes a charge-transfer-based crossbar, where the accumulation is performed by counting the transferred charges into capacitors. Thanks to the time-discrete property of the charge transfer and adaptive body-biasing (ABB) current generator, the entire proposed crossbar is almost fully dynamic and very insensitive to parasitic wire resistance without DAC/ADC needed. In addition, adaptive reference technique is applied to realize a self-adjustable operating range for quantitated neural network computations. The proposed crossbar prototype is designed with 22nm-FDSOI and post-simulated with a size of 128 times 128. A computation and power efficiency of 1024GOP/s and 78TOPS/w is achieved for computation with 4-bit inputs, 1-bit weight, and 4-bit output. Both computation-and power efficiency can be further enhanced by enlarging the crossbars' size without any significant loss of the computation precision.
KW - Compute-In-Memory (CIM)
KW - adaptive body biasing (ABB)
KW - charge-transfer-based crossbar
KW - non von Neumann architecture
KW - wire resistance
UR - http://www.scopus.com/inward/record.url?scp=85142508831&partnerID=8YFLogxK
U2 - 10.1109/ISCAS48785.2022.9937243
DO - 10.1109/ISCAS48785.2022.9937243
M3 - Conference contribution
AN - SCOPUS:85142508831
T3 - Proceedings - IEEE International Symposium on Circuits and Systems
SP - 1397
EP - 1401
BT - IEEE International Symposium on Circuits and Systems, ISCAS 2022
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2022 IEEE International Symposium on Circuits and Systems, ISCAS 2022
Y2 - 27 May 2022 through 1 June 2022
ER -