A Concise, Architecture-Focused ASIP Modeling Approach for Instruction Set Simulators

Virtual prototyping and instruction set simulation are used in the field of rapid prototyping for early design verification and a head-start on software development. With new ISAs such as RISC-V, which focus on openness and extensibility to define more ASIPs, easy-to-extend ASIP ISSs and modeling languages have become key tools for architectural exploration. The work presented in this paper provides a middle ground between existing modeling approaches; where either only very specific parts of a target core can be customized or the entire system in all its details must be described. We present a modeling strategy flexible enough to describe an entire ASIP in a manner that is still concise, readable, and extendable. For this, we generalize as many details as possible and only capture architecturally relevant parts in the system model. To prove and verify our concept, we use it to extend an open-source RISC-V ISS and its model-generation toolchain by important core-close behaviors: trap handling, virtual memory, and semihosting. For evaluation, we built a datasheetaccurate RV64GC core with an Sv39 MMU and verified it against the RISC-V instruction test suite.