A Comprehensive Survey on Electronic Design Automation and Graph Neural Networks: Theory and Applications

Daniela Sánchez, Lorenzo Servadei, Gamze Naz Kiprit, Robert Wille, Wolfgang Ecker

Research output: Contribution to journalArticlepeer-review

16 Scopus citations

Abstract

Driven by Moore's law, the chip design complexity is steadily increasing. Electronic Design Automation (EDA) has been able to cope with the challenging very large-scale integration process, assuring scalability, reliability, and proper time-to-market. However, EDA approaches are time and resource demanding, and they often do not guarantee optimal solutions. To alleviate these, Machine Learning (ML) has been incorporated into many stages of the design flow, such as in placement and routing. Many solutions employ Euclidean data and ML techniques without considering that many EDA objects are represented naturally as graphs. The trending Graph Neural Networks (GNNs) are an opportunity to solve EDA problems directly using graph structures for circuits, intermediate Register Transfer Levels, and netlists. In this article, we present a comprehensive review of the existing works linking the EDA flow for chip design and GNNs. We map those works to a design pipeline by defining graphs, tasks, and model types. Furthermore, we analyze their practical implications and outcomes. We conclude by summarizing challenges faced when applying GNNs within the EDA design flow.

Original languageEnglish
Article number3543853
JournalACM Transactions on Design Automation of Electronic Systems
Volume28
Issue number2
DOIs
StatePublished - 21 Feb 2023

Keywords

  • Electronic Design Automation
  • Graph Neural Networks
  • machine learning
  • register-transfer level
  • very large-scale integration

Fingerprint

Dive into the research topics of 'A Comprehensive Survey on Electronic Design Automation and Graph Neural Networks: Theory and Applications'. Together they form a unique fingerprint.

Cite this