TY - GEN
T1 - A Compact Model of Negative Bias Temperature Instability Suitable for Gate-Level Circuit Simulation
AU - Liu, Xu
AU - Bernardini, Alessandro
AU - Schlichtmann, Ulf
AU - Zhou, Xing
N1 - Publisher Copyright:
© 2019 IEEE.
PY - 2019/4/23
Y1 - 2019/4/23
N2 - Negative Bias Temperature Instability (NBTI) has been a reliability concern with CMOS technology scaling. The threshold voltage of a p-MOSFET degrades, resulting in the delay increment of a digital gate since more time is needed to charge the output load. The gate-level timing model takes the threshold voltage shift as an input. Therefore, an accurate and fast simulation method for NBTI is important. In this paper, a new approach to efficiently yet accurately compute the threshold voltage degradation due to AC-mode NBTI is proposed.
AB - Negative Bias Temperature Instability (NBTI) has been a reliability concern with CMOS technology scaling. The threshold voltage of a p-MOSFET degrades, resulting in the delay increment of a digital gate since more time is needed to charge the output load. The gate-level timing model takes the threshold voltage shift as an input. Therefore, an accurate and fast simulation method for NBTI is important. In this paper, a new approach to efficiently yet accurately compute the threshold voltage degradation due to AC-mode NBTI is proposed.
KW - NBTI
KW - Reliability
KW - compact modeling
UR - http://www.scopus.com/inward/record.url?scp=85065183657&partnerID=8YFLogxK
U2 - 10.1109/ISQED.2019.8697494
DO - 10.1109/ISQED.2019.8697494
M3 - Conference contribution
AN - SCOPUS:85065183657
T3 - Proceedings - International Symposium on Quality Electronic Design, ISQED
SP - 76
EP - 80
BT - Proceedings of the 20th International Symposium on Quality Electronic Design, ISQED 2019
PB - IEEE Computer Society
T2 - 20th International Symposium on Quality Electronic Design, ISQED 2019
Y2 - 6 March 2019 through 7 March 2019
ER -