TY - JOUR
T1 - A compact model for NBTI degradation and recovery under use-profile variations and its application to aging analysis of digital integrated circuits
AU - Kleeberger, Veit B.
AU - Barke, Martin
AU - Werner, Christoph
AU - Schmitt-Landsiedel, Doris
AU - Schlichtmann, Ulf
N1 - Funding Information:
This work was supported in part by the German Research Foundation (DFG) as part of the priority program “Dependable Embedded Systems” (SPP 1500 – http://spp1500.itec.kit.edu ).
PY - 2014
Y1 - 2014
N2 - We present an aging analysis which considers variations in chip environment and workload as they are caused by dynamic voltage or frequency scaling, power-down modes, etc. Therefore, we developed a model for NBTI degradation and recovery based on trapping/detrapping. Our model accurately describes the relaxation during detrapping, the quasi-permanent degradation and shows good agreement with measurements from a 65 nm technology. The aging analysis utilizes this model to consider variations in environment and workload. Results show that our analysis can be used for system-level design decisions and reduces substantially estimated degradation.
AB - We present an aging analysis which considers variations in chip environment and workload as they are caused by dynamic voltage or frequency scaling, power-down modes, etc. Therefore, we developed a model for NBTI degradation and recovery based on trapping/detrapping. Our model accurately describes the relaxation during detrapping, the quasi-permanent degradation and shows good agreement with measurements from a 65 nm technology. The aging analysis utilizes this model to consider variations in environment and workload. Results show that our analysis can be used for system-level design decisions and reduces substantially estimated degradation.
UR - http://www.scopus.com/inward/record.url?scp=84901601885&partnerID=8YFLogxK
U2 - 10.1016/j.microrel.2013.12.002
DO - 10.1016/j.microrel.2013.12.002
M3 - Article
AN - SCOPUS:84901601885
SN - 0026-2714
VL - 54
SP - 1083
EP - 1089
JO - Microelectronics Reliability
JF - Microelectronics Reliability
IS - 6-7
ER -