TY - GEN
T1 - A cascadable integrated bistatic six-port transceiver at 60 GHz in a 130-nm BiCMOS technology for SIMO-radar applications
AU - Voelkel, Matthias
AU - Pechmann, Stefan
AU - Hussein, Eissa Mohamed
AU - Kissinger, Dietmar
AU - Weigel, Robert
AU - Hagelauer, Amelie
N1 - Publisher Copyright:
© 2019 IEEE.
PY - 2019/12
Y1 - 2019/12
N2 - In this paper a 60 GHz cascadable bistatic integrated interferometric transceiver for SIMO radar applications is presented. The integrated transceiver has been designed in a 0.13 μm SiGe BiCMOS technology (SG13G2) from the institute innovations for high performance microelectronics (IHP). The System includes a 15 GHz buffer stage, a low noise amplifier, a passive interferometric six-port structure, several detectors and amplifiers as well as a digital interface. The chip has a size of 2.75 mm x 1.15 mm and a maximum power consumption of 525 mW from a 3.3 V power supply. The 15 GHz frequency input is multiplied to reach a 60 GHz signal at a minimum input power of-40 dBm. The chip delivers a maximum output power of 10.2 dBm. A digital interface adjusts the output power between-22 and 10, 2 dBm at an output frequency of 60 GHz. The reference input power of the six-port and the RF input power could be adjusted in a range of 13.2 dB. The maximum P1dBis at-24.1 dBm. The measured power detector sensitivity is 7090 V/W. The standard deviation of the phase measurement is 0.025 rad.
AB - In this paper a 60 GHz cascadable bistatic integrated interferometric transceiver for SIMO radar applications is presented. The integrated transceiver has been designed in a 0.13 μm SiGe BiCMOS technology (SG13G2) from the institute innovations for high performance microelectronics (IHP). The System includes a 15 GHz buffer stage, a low noise amplifier, a passive interferometric six-port structure, several detectors and amplifiers as well as a digital interface. The chip has a size of 2.75 mm x 1.15 mm and a maximum power consumption of 525 mW from a 3.3 V power supply. The 15 GHz frequency input is multiplied to reach a 60 GHz signal at a minimum input power of-40 dBm. The chip delivers a maximum output power of 10.2 dBm. A digital interface adjusts the output power between-22 and 10, 2 dBm at an output frequency of 60 GHz. The reference input power of the six-port and the RF input power could be adjusted in a range of 13.2 dB. The maximum P1dBis at-24.1 dBm. The measured power detector sensitivity is 7090 V/W. The standard deviation of the phase measurement is 0.025 rad.
KW - Bistatic
KW - Industrial radar
KW - Integrated transceiver
KW - Interferometric radar
KW - MMIC
KW - Millimeter wave circuits
KW - SIMO radar
KW - SiGe biCMOS
KW - Six-port
KW - System-on-chip (SoC)
UR - https://www.scopus.com/pages/publications/85082993039
U2 - 10.1109/APMC46564.2019.9038421
DO - 10.1109/APMC46564.2019.9038421
M3 - Conference contribution
AN - SCOPUS:85082993039
T3 - Asia-Pacific Microwave Conference Proceedings, APMC
SP - 622
EP - 624
BT - Proceedings of the 2019 IEEE Asia-Pacific Microwave Conference, APMC 2019
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2019 IEEE Asia-Pacific Microwave Conference, APMC 2019
Y2 - 10 December 2019 through 13 December 2019
ER -