TY - GEN

T1 - A bit level algorithm for subspace tracking

AU - Götze, J.

AU - Ali, M.

AU - Nossek, J. A.

N1 - Publisher Copyright:
© 1993 IEEE.

PY - 1993

Y1 - 1993

N2 - The presented EVD-based subspace tracking algorithm is highly suited for VLSI-implementation. It is based on the binary data representation of the CORDIC scheme combined with the use of approximate rotations. The different modifications of the original EVD-based subspace tracking algorithm can be interlaced, i.e. the number of rotations (sweeps) executed after each rank-1-update and the number of applied best CORDIC angles can be exchanged. The simulations show that it is usually advantageous to work with π = 2 and to adjust the number of rotations/sweeps executed after each update to the specific application, since for small rotation angles (generally present in tracking applications) π = 2 already yields an almost exact rotation.

AB - The presented EVD-based subspace tracking algorithm is highly suited for VLSI-implementation. It is based on the binary data representation of the CORDIC scheme combined with the use of approximate rotations. The different modifications of the original EVD-based subspace tracking algorithm can be interlaced, i.e. the number of rotations (sweeps) executed after each rank-1-update and the number of applied best CORDIC angles can be exchanged. The simulations show that it is usually advantageous to work with π = 2 and to adjust the number of rotations/sweeps executed after each update to the specific application, since for small rotation angles (generally present in tracking applications) π = 2 already yields an almost exact rotation.

UR - http://www.scopus.com/inward/record.url?scp=1942437155&partnerID=8YFLogxK

U2 - 10.1109/VLSISP.1993.404471

DO - 10.1109/VLSISP.1993.404471

M3 - Conference contribution

AN - SCOPUS:1942437155

T3 - Proceedings of IEEE Workshop on VLSI Signal Processing VI, VLSISP 1993

SP - 352

EP - 360

BT - Proceedings of IEEE Workshop on VLSI Signal Processing VI, VLSISP 1993

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 6th IEEE Workshop on VLSI Signal Processing, VLSISP 1993

Y2 - 20 October 1993 through 22 October 1993

ER -