A 9-bit, 1.08ps resolution two-step time-to-digital converter in 65 nm CMOS for time-mode ADC

Junjie Kong; Stephan Henzler; Doris Schmitt-Landsiedel; Liter Siek

doi:10.1109/APCCAS.2016.7803972

A 9-bit, 1.08ps resolution two-step time-to-digital converter in 65 nm CMOS for time-mode ADC

Junjie Kong, Stephan Henzler, Doris Schmitt-Landsiedel, Liter Siek

Medicine and Health

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

3 Scopus citations

Abstract

This paper presents the design of a 9-bit, Two-Step Time-to-Digital Converter (TDC) in 65 nm CMOS for the application in a time-mode ADC. The proposed TDC uses body-biasing in the fine TDC to obtain the resolution of the entire TDC, which is simulated to be 1.08 ps. With a dynamic range of 555 ps, the maximum conversion time between START and the availability of results is 2.7 ns. The proposed TDC consumes 0.667 mW at 200 MHz, with a FoM of 0.0065 pJ/conversion. The DNL and INL are simulated to be -0.097/0.2 LSB and -0.12/0.41 LSB respectively.

Original language	English
Title of host publication	2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	348-351
Number of pages	4
ISBN (Electronic)	9781509015702
DOIs	https://doi.org/10.1109/APCCAS.2016.7803972
State	Published - 3 Jan 2017
Event	2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016 - Jeju, Korea, Republic of Duration: 25 Oct 2016 → 28 Oct 2016

Publication series

Name	2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016

Conference

Conference	2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016
Country/Territory	Korea, Republic of
City	Jeju
Period	25/10/16 → 28/10/16

Keywords

Time-to-digital Converter (TDC)
body-biasing
time-mode ADC
two-step architecture
vernier TDC

Access to Document

10.1109/APCCAS.2016.7803972

Cite this

Kong, J., Henzler, S., Schmitt-Landsiedel, D., & Siek, L. (2017). A 9-bit, 1.08ps resolution two-step time-to-digital converter in 65 nm CMOS for time-mode ADC. In 2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016 (pp. 348-351). Article 7803972 (2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/APCCAS.2016.7803972

Kong, Junjie ; Henzler, Stephan ; Schmitt-Landsiedel, Doris et al. / A 9-bit, 1.08ps resolution two-step time-to-digital converter in 65 nm CMOS for time-mode ADC. 2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016. Institute of Electrical and Electronics Engineers Inc., 2017. pp. 348-351 (2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016).

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title = "A 9-bit, 1.08ps resolution two-step time-to-digital converter in 65 nm CMOS for time-mode ADC",

abstract = "This paper presents the design of a 9-bit, Two-Step Time-to-Digital Converter (TDC) in 65 nm CMOS for the application in a time-mode ADC. The proposed TDC uses body-biasing in the fine TDC to obtain the resolution of the entire TDC, which is simulated to be 1.08 ps. With a dynamic range of 555 ps, the maximum conversion time between START and the availability of results is 2.7 ns. The proposed TDC consumes 0.667 mW at 200 MHz, with a FoM of 0.0065 pJ/conversion. The DNL and INL are simulated to be -0.097/0.2 LSB and -0.12/0.41 LSB respectively.",

keywords = "Time-to-digital Converter (TDC), body-biasing, time-mode ADC, two-step architecture, vernier TDC",

author = "Junjie Kong and Stephan Henzler and Doris Schmitt-Landsiedel and Liter Siek",

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Kong, J, Henzler, S, Schmitt-Landsiedel, D & Siek, L 2017, A 9-bit, 1.08ps resolution two-step time-to-digital converter in 65 nm CMOS for time-mode ADC. in 2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016., 7803972, 2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016, Institute of Electrical and Electronics Engineers Inc., pp. 348-351, 2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016, Jeju, Korea, Republic of, 25/10/16. https://doi.org/10.1109/APCCAS.2016.7803972

A 9-bit, 1.08ps resolution two-step time-to-digital converter in 65 nm CMOS for time-mode ADC. / Kong, Junjie; Henzler, Stephan; Schmitt-Landsiedel, Doris et al.
2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016. Institute of Electrical and Electronics Engineers Inc., 2017. p. 348-351 7803972 (2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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N2 - This paper presents the design of a 9-bit, Two-Step Time-to-Digital Converter (TDC) in 65 nm CMOS for the application in a time-mode ADC. The proposed TDC uses body-biasing in the fine TDC to obtain the resolution of the entire TDC, which is simulated to be 1.08 ps. With a dynamic range of 555 ps, the maximum conversion time between START and the availability of results is 2.7 ns. The proposed TDC consumes 0.667 mW at 200 MHz, with a FoM of 0.0065 pJ/conversion. The DNL and INL are simulated to be -0.097/0.2 LSB and -0.12/0.41 LSB respectively.

AB - This paper presents the design of a 9-bit, Two-Step Time-to-Digital Converter (TDC) in 65 nm CMOS for the application in a time-mode ADC. The proposed TDC uses body-biasing in the fine TDC to obtain the resolution of the entire TDC, which is simulated to be 1.08 ps. With a dynamic range of 555 ps, the maximum conversion time between START and the availability of results is 2.7 ns. The proposed TDC consumes 0.667 mW at 200 MHz, with a FoM of 0.0065 pJ/conversion. The DNL and INL are simulated to be -0.097/0.2 LSB and -0.12/0.41 LSB respectively.

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Kong J, Henzler S, Schmitt-Landsiedel D, Siek L. A 9-bit, 1.08ps resolution two-step time-to-digital converter in 65 nm CMOS for time-mode ADC. In 2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016. Institute of Electrical and Electronics Engineers Inc. 2017. p. 348-351. 7803972. (2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016). doi: 10.1109/APCCAS.2016.7803972

A 9-bit, 1.08ps resolution two-step time-to-digital converter in 65 nm CMOS for time-mode ADC

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Keywords

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