A 65 nm test structure for SRAM device variability and NBTI statistics

We present the results of a test structure that allows to measure the variation of SRAM p-MOS and n-MOS transistors in a dense environment and to apply Negative Bias Temperature Instability (NBTI) stress on the p-MOS transistors. The threshold voltage (V_th) and drain current (I_d) distributions of p-MOS SRAM transistors pre- and post-NBTI stress are measured and analyzed. The probability density functions (PDF) of both transistor parameters V_th and I_d follow a Gaussian distribution pre- and post-NBTI stress, but the difference in the transistor parameters of an individual device is not Gaussian distributed. The standard deviation in the difference of V_th is about 50% of the mean for the small SRAM p-MOS transistor. The impact of the additional variation induced by NBTI stress is shown for the static noise margin of a 6T SRAM cell.