A 60 GHz 30.5% PAE Differential Stacked PA with Second Harmonic Control in 45 nm PD-SOI CMOS

Radu Ciocovean, Robert Weigel, Amelie Hagelauer, Vadim Issakov

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

4 Scopus citations

Abstract

This paper presents a 60 GHz highly efficient single-stage differential stacked Class AB power amplifier (PA) with second harmonic control. The circuit has been realized in a 45 nm PD-SOI CMOS technology. Measurement results show that the power amplifier achieves a maximum output power (Pmax) of 15.3 dBm with a competitive maximum power-added efficiency (PAEmax) of 30.5 % at 60 GHz. The output-referred 1-dB compression point (OP1dB) is 9.5 dBm. Furthermore, the circuit draws 40mA from a 1.8 V supply and the chip core size is 0. 36mmx0.35 mm.

Original languageEnglish
Title of host publication2019 IEEE 19th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, SiRF 2019
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781538659502
DOIs
StatePublished - 7 May 2019
Externally publishedYes
Event19th IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, SiRF 2019 - Orlando, United States
Duration: 20 Jan 201923 Jan 2019

Publication series

Name2019 IEEE 19th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, SiRF 2019

Conference

Conference19th IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, SiRF 2019
Country/TerritoryUnited States
CityOrlando
Period20/01/1923/01/19

Keywords

  • High-Efficiency
  • High-Power
  • PD-SOI
  • Power Amplifier

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