A 6 GHz RO PLL with -285 dB FOM_{Jitter-N-Area}, 130 fs RMS jitter and 0.0016 mm² Area

This paper presents a Sampling Phase Locked Loop (SPLL) with a complementary, cross-coupled, current-starved Ring Oscillator (RO). The focus is shifted away from optimizing the subcomponents to optimizing the contribution of the individual blocks to the phase noise at the PLL output. With a reference clock of 3 GHz, a bandwidth above 200 MHz is attained. This high bandwidth cuts the VCO phase noise to a low level. Our design proposes a novel integral control path using 20 analog control voltages coupled with a proportional path using direct sampling to achieve an in-band noise of -120 dBc/Hz at 1 MHz offset frequency. The proposed SPLL has a Jitter-Power FOM of -254 dB, comparable to the best-in-class published LC oscillator PLLs [1]-[3], and is approximately 10 dB better than state-of-the-art RO PLLs [4]-[7]. The new integral path of the PLL makes it possible to shrink the area to 40μm × 40 μm. This area is more than a factor 14 smaller than all recently published PLLs [1]-[7], resulting in a FOMjitter-N-Area of -285 dB.