A 2 GHz 244 fs-Resolution 1.2 ps-Peak-INL Edge Interpolator-Based Digital-to-Time Converter in 28 nm CMOS

Sebastian Sievert; Ofir Degani; Assaf Ben-Bassat; Rotem Banin; Ashoke Ravi; Wolfgang Thomann; Bernd Ulrich Klepser; Zdravko Boos; Doris Schmitt-Landsiedel

doi:10.1109/JSSC.2016.2592620

A 2 GHz 244 fs-Resolution 1.2 ps-Peak-INL Edge Interpolator-Based Digital-to-Time Converter in 28 nm CMOS

Sebastian Sievert, Ofir Degani, Assaf Ben-Bassat, Rotem Banin, Ashoke Ravi, Wolfgang Thomann, Bernd Ulrich Klepser, Zdravko Boos, Doris Schmitt-Landsiedel

Medicine and Health

Research output: Contribution to journal › Article › peer-review

68 Scopus citations

Abstract

This paper presents a 2 GHz digital-to-time converter (DTC) with 244 fs time resolution. The DTC consists of a multi-modulus divider (MMD) and a phase interpolator (PI) as coarse and fine tuning blocks, respectively. Control logic is implemented to prevent shoot-through current during the interpolation process in order to linearize the PI. The measured DTC's peak integral nonlinearity (INL) is 1.2 ps and limited by the PI. The interpolation process is analyzed in detail, describing the root cause of the nonlinearity and indicating key parameters to improve it. Furthermore, a measurement method for DTCs is presented that enables femtosecond accuracy. The DTC has been implemented in standard 28 nm CMOS technology.

Original language	English
Article number	7548314
Pages (from-to)	2992-3004
Number of pages	13
Journal	IEEE Journal of Solid-State Circuits
Volume	51
Issue number	12
DOIs	https://doi.org/10.1109/JSSC.2016.2592620
State	Published - Dec 2016

Keywords

DNL
DPC
DTC
Digital-to-phase converter
INL
PI
digital-to-time converter
edge interpolator
phase interpolator

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10.1109/JSSC.2016.2592620

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title = "A 2 GHz 244 fs-Resolution 1.2 ps-Peak-INL Edge Interpolator-Based Digital-to-Time Converter in 28 nm CMOS",

abstract = "This paper presents a 2 GHz digital-to-time converter (DTC) with 244 fs time resolution. The DTC consists of a multi-modulus divider (MMD) and a phase interpolator (PI) as coarse and fine tuning blocks, respectively. Control logic is implemented to prevent shoot-through current during the interpolation process in order to linearize the PI. The measured DTC's peak integral nonlinearity (INL) is 1.2 ps and limited by the PI. The interpolation process is analyzed in detail, describing the root cause of the nonlinearity and indicating key parameters to improve it. Furthermore, a measurement method for DTCs is presented that enables femtosecond accuracy. The DTC has been implemented in standard 28 nm CMOS technology.",

keywords = "DNL, DPC, DTC, Digital-to-phase converter, INL, PI, digital-to-time converter, edge interpolator, phase interpolator",

author = "Sebastian Sievert and Ofir Degani and Assaf Ben-Bassat and Rotem Banin and Ashoke Ravi and Wolfgang Thomann and Klepser, {Bernd Ulrich} and Zdravko Boos and Doris Schmitt-Landsiedel",

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year = "2016",

month = dec,

doi = "10.1109/JSSC.2016.2592620",

language = "English",

volume = "51",

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AU - Sievert, Sebastian

AU - Degani, Ofir

AU - Ben-Bassat, Assaf

AU - Banin, Rotem

AU - Ravi, Ashoke

AU - Thomann, Wolfgang

AU - Klepser, Bernd Ulrich

AU - Boos, Zdravko

AU - Schmitt-Landsiedel, Doris

PY - 2016/12

Y1 - 2016/12

N2 - This paper presents a 2 GHz digital-to-time converter (DTC) with 244 fs time resolution. The DTC consists of a multi-modulus divider (MMD) and a phase interpolator (PI) as coarse and fine tuning blocks, respectively. Control logic is implemented to prevent shoot-through current during the interpolation process in order to linearize the PI. The measured DTC's peak integral nonlinearity (INL) is 1.2 ps and limited by the PI. The interpolation process is analyzed in detail, describing the root cause of the nonlinearity and indicating key parameters to improve it. Furthermore, a measurement method for DTCs is presented that enables femtosecond accuracy. The DTC has been implemented in standard 28 nm CMOS technology.

AB - This paper presents a 2 GHz digital-to-time converter (DTC) with 244 fs time resolution. The DTC consists of a multi-modulus divider (MMD) and a phase interpolator (PI) as coarse and fine tuning blocks, respectively. Control logic is implemented to prevent shoot-through current during the interpolation process in order to linearize the PI. The measured DTC's peak integral nonlinearity (INL) is 1.2 ps and limited by the PI. The interpolation process is analyzed in detail, describing the root cause of the nonlinearity and indicating key parameters to improve it. Furthermore, a measurement method for DTCs is presented that enables femtosecond accuracy. The DTC has been implemented in standard 28 nm CMOS technology.

KW - DNL

KW - DPC

KW - DTC

KW - Digital-to-phase converter

KW - INL

KW - PI

KW - digital-to-time converter

KW - edge interpolator

KW - phase interpolator

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SP - 2992

EP - 3004

JO - IEEE Journal of Solid-State Circuits

JF - IEEE Journal of Solid-State Circuits

IS - 12

M1 - 7548314

ER -

A 2 GHz 244 fs-Resolution 1.2 ps-Peak-INL Edge Interpolator-Based Digital-to-Time Converter in 28 nm CMOS

Abstract

Keywords

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