TY - GEN
T1 - A 0.6V Multi-VT current mirror differential OTA
AU - Bargagli-Stoffi, A.
AU - Sauerbrey, J.
AU - Wang, J.
AU - Shrivastava, R.
AU - Schmitt-Landsiedel, D.
PY - 2005
Y1 - 2005
N2 - A low power fully differential transconductance amplifier with rail-to-rail outputs, operating from a single 0.6V supply and simulated in a 90nm CMOS standard process is presented. Since the scaling of the threshold voltage does not proportionally follow the supply voltage scaling, transistors are driven in moderate inversion and their minimum drain source voltage becomes a significant fraction of the power supply. Through a straightforward analysis of a low voltage current mirror, the obtainable Improvements due to the use of the multi-VT option of the process are highlighted. The amplifier, whose transistors operate in moderate inversion, presents a unity gain bandwidth of 100MHz with a power consumption of 90μW.
AB - A low power fully differential transconductance amplifier with rail-to-rail outputs, operating from a single 0.6V supply and simulated in a 90nm CMOS standard process is presented. Since the scaling of the threshold voltage does not proportionally follow the supply voltage scaling, transistors are driven in moderate inversion and their minimum drain source voltage becomes a significant fraction of the power supply. Through a straightforward analysis of a low voltage current mirror, the obtainable Improvements due to the use of the multi-VT option of the process are highlighted. The amplifier, whose transistors operate in moderate inversion, presents a unity gain bandwidth of 100MHz with a power consumption of 90μW.
UR - http://www.scopus.com/inward/record.url?scp=33749076627&partnerID=8YFLogxK
U2 - 10.1109/ISSCS.2005.1509908
DO - 10.1109/ISSCS.2005.1509908
M3 - Conference contribution
AN - SCOPUS:33749076627
SN - 0780390296
SN - 9780780390294
T3 - ISSCS 2005: International Symposium on Signals, Circuits and Systems - Proceedings
SP - 279
EP - 282
BT - ISSCS 2005
T2 - ISSCS 2005: International Symposium on Signals, Circuits and Systems
Y2 - 14 July 2005 through 15 July 2005
ER -