A 0.5V, 1μW successive approximation ADC

Jens Sauerbrey; Doris Schmitt-Landsiedel; Roland Thewes

A 0.5V, 1μW successive approximation ADC

Jens Sauerbrey, Doris Schmitt-Landsiedel, Roland Thewes

Medicine and Health

Infineon Technologies AG

Research output: Contribution to journal › Conference article › peer-review

21 Scopus citations

Abstract

A successive approximation analog-to-digital converter (ADC) is presented operating at ultra low supply voltages. The circuit is realized in a 0.18μm CMOS technology. Neither low-V_Tdevices nor voltage boosting techniques are used. All voltage levels are between supply voltage (VDD) and ground (VSS). A passive sample-and-hold stage and an capacitor-based digital-to-analog converter (DAC) are used to avoid application of opamps, since opamp operation requires higher values for the lowest possible supply voltage. The ADC has a signal-to-noise-and-distortion ratio (SNDR) of 51.2dB and 43.3dB for supply voltages of 1V and 0.5V, at sampling rates of 150kS/s and 4.1kS/s and power consumptions of 30μW and 0.85μW, respectively. Proper operation is achieved down to a supply voltage of 0.4V.

Original language	English
Article number	1471512
Pages (from-to)	247-250
Number of pages	4
Journal	European Solid-State Circuits Conference
State	Published - 2002
Event	28th European Solid-State Circuits Conference, ESSCIRC 2002 - Florence, Italy Duration: 24 Sep 2002 → 26 Sep 2002

Cite this

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title = "A 0.5V, 1μW successive approximation ADC",

abstract = "A successive approximation analog-to-digital converter (ADC) is presented operating at ultra low supply voltages. The circuit is realized in a 0.18μm CMOS technology. Neither low-VTdevices nor voltage boosting techniques are used. All voltage levels are between supply voltage (VDD) and ground (VSS). A passive sample-and-hold stage and an capacitor-based digital-to-analog converter (DAC) are used to avoid application of opamps, since opamp operation requires higher values for the lowest possible supply voltage. The ADC has a signal-to-noise-and-distortion ratio (SNDR) of 51.2dB and 43.3dB for supply voltages of 1V and 0.5V, at sampling rates of 150kS/s and 4.1kS/s and power consumptions of 30μW and 0.85μW, respectively. Proper operation is achieved down to a supply voltage of 0.4V.",

author = "Jens Sauerbrey and Doris Schmitt-Landsiedel and Roland Thewes",

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language = "English",

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journal = "European Solid-State Circuits Conference",

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T1 - A 0.5V, 1μW successive approximation ADC

AU - Sauerbrey, Jens

AU - Schmitt-Landsiedel, Doris

AU - Thewes, Roland

PY - 2002

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N2 - A successive approximation analog-to-digital converter (ADC) is presented operating at ultra low supply voltages. The circuit is realized in a 0.18μm CMOS technology. Neither low-VTdevices nor voltage boosting techniques are used. All voltage levels are between supply voltage (VDD) and ground (VSS). A passive sample-and-hold stage and an capacitor-based digital-to-analog converter (DAC) are used to avoid application of opamps, since opamp operation requires higher values for the lowest possible supply voltage. The ADC has a signal-to-noise-and-distortion ratio (SNDR) of 51.2dB and 43.3dB for supply voltages of 1V and 0.5V, at sampling rates of 150kS/s and 4.1kS/s and power consumptions of 30μW and 0.85μW, respectively. Proper operation is achieved down to a supply voltage of 0.4V.

AB - A successive approximation analog-to-digital converter (ADC) is presented operating at ultra low supply voltages. The circuit is realized in a 0.18μm CMOS technology. Neither low-VTdevices nor voltage boosting techniques are used. All voltage levels are between supply voltage (VDD) and ground (VSS). A passive sample-and-hold stage and an capacitor-based digital-to-analog converter (DAC) are used to avoid application of opamps, since opamp operation requires higher values for the lowest possible supply voltage. The ADC has a signal-to-noise-and-distortion ratio (SNDR) of 51.2dB and 43.3dB for supply voltages of 1V and 0.5V, at sampling rates of 150kS/s and 4.1kS/s and power consumptions of 30μW and 0.85μW, respectively. Proper operation is achieved down to a supply voltage of 0.4V.

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M3 - Conference article

AN - SCOPUS:84893713935

SN - 1930-8833

SP - 247

EP - 250

JO - European Solid-State Circuits Conference

JF - European Solid-State Circuits Conference

M1 - 1471512

T2 - 28th European Solid-State Circuits Conference, ESSCIRC 2002

Y2 - 24 September 2002 through 26 September 2002

ER -

A 0.5V, 1μW successive approximation ADC

Abstract

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