A 0.5-V 1-μ W successive approximation ADC

Jens Sauerbrey; Doris Schmitt-Landsiedel; Roland Thewes

doi:10.1109/JSSC.2003.813217

A 0.5-V 1-μ W successive approximation ADC

Jens Sauerbrey
, Doris Schmitt-Landsiedel
, Roland Thewes

Medicine and Health

Infineon Technologies AG

Research output: Contribution to journal › Article › peer-review

187 Scopus citations

Abstract

A successive approximation analog-to-digital converter (ADC) is presented operating at ultralow supply voltages. The circuit is realized in a 0.18-μm standard CMOS technology. Neither low-V_T devices nor voltage boosting techniques are used. All voltage levels are between supply voltage V_DD and ground V_SS. A passive sample-and-hold stage and a capacitor-based digital-to-analog converter are used to avoid application of operational amplifiers, since opamp operation requires higher values for the lowest possible supply voltage. The ADC has signal-to-noise-and-distortion ratios of 51.2 and 43.3 dB for supply voltages of 1 and 0.5 V, at sampling rates of 150 and 4.1 kS/s and power consumptions of 30 and 0.85 μW, respectively. Proper operation is achieved down to a supply voltage of 0.4 V.

Original language	English
Pages (from-to)	1261-1265
Number of pages	5
Journal	IEEE Journal of Solid-State Circuits
Volume	38
Issue number	7
DOIs	https://doi.org/10.1109/JSSC.2003.813217
State	Published - Jul 2003

Keywords

Analog-to-digital converters (ADCs)
CMOS analog integrated circuits
Low power
Low supply voltage
Successive approximation
Switched-capacitor circuits

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10.1109/JSSC.2003.813217

Cite this

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title = "A 0.5-V 1-μ W successive approximation ADC",

abstract = "A successive approximation analog-to-digital converter (ADC) is presented operating at ultralow supply voltages. The circuit is realized in a 0.18-μm standard CMOS technology. Neither low-VT devices nor voltage boosting techniques are used. All voltage levels are between supply voltage VDD and ground VSS. A passive sample-and-hold stage and a capacitor-based digital-to-analog converter are used to avoid application of operational amplifiers, since opamp operation requires higher values for the lowest possible supply voltage. The ADC has signal-to-noise-and-distortion ratios of 51.2 and 43.3 dB for supply voltages of 1 and 0.5 V, at sampling rates of 150 and 4.1 kS/s and power consumptions of 30 and 0.85 μW, respectively. Proper operation is achieved down to a supply voltage of 0.4 V.",

keywords = "Analog-to-digital converters (ADCs), CMOS analog integrated circuits, Low power, Low supply voltage, Successive approximation, Switched-capacitor circuits",

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AU - Schmitt-Landsiedel, Doris

AU - Thewes, Roland

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N2 - A successive approximation analog-to-digital converter (ADC) is presented operating at ultralow supply voltages. The circuit is realized in a 0.18-μm standard CMOS technology. Neither low-VT devices nor voltage boosting techniques are used. All voltage levels are between supply voltage VDD and ground VSS. A passive sample-and-hold stage and a capacitor-based digital-to-analog converter are used to avoid application of operational amplifiers, since opamp operation requires higher values for the lowest possible supply voltage. The ADC has signal-to-noise-and-distortion ratios of 51.2 and 43.3 dB for supply voltages of 1 and 0.5 V, at sampling rates of 150 and 4.1 kS/s and power consumptions of 30 and 0.85 μW, respectively. Proper operation is achieved down to a supply voltage of 0.4 V.

AB - A successive approximation analog-to-digital converter (ADC) is presented operating at ultralow supply voltages. The circuit is realized in a 0.18-μm standard CMOS technology. Neither low-VT devices nor voltage boosting techniques are used. All voltage levels are between supply voltage VDD and ground VSS. A passive sample-and-hold stage and a capacitor-based digital-to-analog converter are used to avoid application of operational amplifiers, since opamp operation requires higher values for the lowest possible supply voltage. The ADC has signal-to-noise-and-distortion ratios of 51.2 and 43.3 dB for supply voltages of 1 and 0.5 V, at sampling rates of 150 and 4.1 kS/s and power consumptions of 30 and 0.85 μW, respectively. Proper operation is achieved down to a supply voltage of 0.4 V.

KW - Analog-to-digital converters (ADCs)

KW - CMOS analog integrated circuits

KW - Low power

KW - Low supply voltage

KW - Successive approximation

KW - Switched-capacitor circuits

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A 0.5-V 1-μ W successive approximation ADC

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