TY - GEN
T1 - 20nm FinFET-based SRAM cell
T2 - 14th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2017
AU - Karapetyan, Shushanik
AU - Schlichtmann, Ulf
N1 - Publisher Copyright:
© 2017 IEEE.
PY - 2017/7/14
Y1 - 2017/7/14
N2 - The relentless scaling of semiconductor technology has resulted in dramatic performance improvements of Integrated Circuits (ICs). However, traditional planar CMOS technology seems to have reached its limit. To continue with Moore's law, FinFET technology has shown to be a viable solution. Process variations are still relevant, however. Therefore, it is crucial to study their impact on circuit performance. This paper explores design choices for 20nm FinFET-based SRAM cells and analyzes the impact of process variations on the performance characteristics of the SRAM cell.
AB - The relentless scaling of semiconductor technology has resulted in dramatic performance improvements of Integrated Circuits (ICs). However, traditional planar CMOS technology seems to have reached its limit. To continue with Moore's law, FinFET technology has shown to be a viable solution. Process variations are still relevant, however. Therefore, it is crucial to study their impact on circuit performance. This paper explores design choices for 20nm FinFET-based SRAM cells and analyzes the impact of process variations on the performance characteristics of the SRAM cell.
UR - http://www.scopus.com/inward/record.url?scp=85027490585&partnerID=8YFLogxK
U2 - 10.1109/SMACD.2017.7981615
DO - 10.1109/SMACD.2017.7981615
M3 - Conference contribution
AN - SCOPUS:85027490585
T3 - SMACD 2017 - 14th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design
BT - SMACD 2017 - 14th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design
PB - Institute of Electrical and Electronics Engineers Inc.
Y2 - 12 June 2017 through 15 June 2017
ER -