Wait-free message passing protocol for non-coherent shared memory architectures

Isaías A. Comprés Ureña, Michael Gerndt, Carsten Trinitis

Publikation: Beitrag in Buch/Bericht/KonferenzbandKonferenzbeitragBegutachtung

1 Zitat (Scopus)

Abstract

The number of cores in future CPUs is expected to increase steadily. Balanced CPU designs scale hardware cache coherency functionality according to the number of cores, in order to minimize bottlenecks in parallel applications. An alternative approach is to do away with hardware coherence entirely; the Single-chip Cloud Computer (SCC), a 48 core experimental processor from Intel labs, does exactly that. A wait-free protocol for message passing on non-coherent buffers was introduced with the RCKMPI library, in order to support MPI on the SCC. In this work, the message passing performance of the protocol is modeled. Additionally, a port for symmetric multi-processors is introduced and used for comparison with MPICH2-Nemesis and Open MPI. Performance is analyzed based on statistics collected on a 4-dimensional space composed of source rank, target rank, message size and frequency.

OriginalspracheEnglisch
TitelRecent Advances in the Message Passing Interface - 19th European MPI Users' Group Meeting, EuroMPI 2012, Proceedings
Seiten142-152
Seitenumfang11
DOIs
PublikationsstatusVeröffentlicht - 2012
Veranstaltung19th European MPI Users' Group Meeting on Recent Advances in the Message Passing Interface, EuroMPI 2012 - Vienna, Österreich
Dauer: 23 Sept. 201226 Sept. 2012

Publikationsreihe

NameLecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Band7490 LNCS
ISSN (Print)0302-9743
ISSN (elektronisch)1611-3349

Konferenz

Konferenz19th European MPI Users' Group Meeting on Recent Advances in the Message Passing Interface, EuroMPI 2012
Land/GebietÖsterreich
OrtVienna
Zeitraum23/09/1226/09/12

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