Virtual double pulse tests to reduce measuring time and effort in semiconductor loss modeling

Accurate loss models for power semiconductor devices are indispensable for the design of power converters. The estimation of losses is important for the design of the hardware components and the comparison of these devices. This paper proposes a new methodology for creating accurate loss models with less measurement effort than the conventional double pulse test. SPICE models are used to create a trend model of the losses. This trend model is then referenced to the real hardware with a single measurement. The differences between the trend model and the conventionally derived ones are then explored. The models are validated by accurately simulating the switching losses of a high power DC-DC converter. The new model therefore represents the losses in the operating range with the same accuracy as the traditionally ones derived by double pulse test but with considerably lower measurement effort.