VHDL synthesis description portability: The need for level synthesis subsets

Synthesis represents today one of the most important applications of VHDL with a high user demand. Nevertheless, VHDL lacks a standard synthesis methodology and, as a consequence, each synthesis tool imposes its own synthesis methodology on the user. This fact has many disadvantages; the main one is the lack of portability. In this paper, the activities of the European VHDL Synthesis Working Group towards the definition of a Level-0 synthesis subset will be described. The Level-0 subset will constitute a standard subset of VHDL for synthesis applications which will allow description portability between tools as well as design reusability. Their contents will be described and their advantages and limitations commented on.