VHDL-based communication- and synchronization synthesis

Wolfgang Ecker, Manfred Huber

Publikation: KonferenzbeitragPapierBegutachtung

1 Zitat (Scopus)

Abstract

This paper describes an approach for VHDL-based communication and synchronization synthesis. This design step transforms a system level VHDL description into an RT-level description. The idea is, not to synthesize system level implementations of communication and synchronization mechanisms but to perform the synthesis step as a mapping step of an abstract communication or synchronization mechanism to one of a set of RT-level implementations. The major sub-problem, which needed to be solved for the synthesis algorithm was the topology dependent mapping of implementations.

OriginalspracheEnglisch
Seiten458-462
Seitenumfang5
PublikationsstatusVeröffentlicht - 1995
Extern publiziertJa
VeranstaltungProceedings of the 1995 European Design Automation Conference with EURO-VHDL - Brighton, UK
Dauer: 18 Sept. 199522 Sept. 1995

Konferenz

KonferenzProceedings of the 1995 European Design Automation Conference with EURO-VHDL
OrtBrighton, UK
Zeitraum18/09/9522/09/95

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