VHDL 200× - requirements from testbench-view

Matthias Bauer; Wolfgang Ecker; Mike Heuchling

VHDL 200× - requirements from testbench-view

Matthias Bauer, Wolfgang Ecker, Mike Heuchling

Siemens AG

Publikation: Konferenzbeitrag › Papier › Begutachtung

Abstract

Both, requirements for VHDL and restrictions to VHDL standards are discussed by many groups and forums. A problem to be solved is to handle the growing complexity of hardware designs and test environments. Aim of the paper is to support the discussion by defining requirements impacted by modern verification techniques. We focus on performance and modeling aspects from testbench development view. Therefore we consider simulation methodologies, coding styles and in particular VHDL extensions. Further, impacts on VHDL extensions by modern requirement engineering methodologies are dealt with.

Originalsprache	Englisch
Seiten	39-41
Seitenumfang	3
Publikationsstatus	Veröffentlicht - 1998
Extern publiziert	Ja
Veranstaltung	Proceedings of the 1998 International Verilog HDL Conference - Santa Clara, CA, USA Dauer: 16 März 1998 → 19 März 1998

Konferenz

Konferenz	Proceedings of the 1998 International Verilog HDL Conference
Ort	Santa Clara, CA, USA
Zeitraum	16/03/98 → 19/03/98

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T2 - Proceedings of the 1998 International Verilog HDL Conference

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VHDL 200× - requirements from testbench-view

Abstract

Konferenz

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