TY - GEN
T1 - Using hardware software codesign for optimised implementations of high-speed and defence in depth CAESAR finalists
AU - Tempelmeier, Michael
AU - Werner, Maximilian
AU - Sigl, Georg
N1 - Publisher Copyright:
© 2019 IEEE.
PY - 2019/5
Y1 - 2019/5
N2 - In this work, we present five optimised implementations on a Xilinx-Zynq7200 SoC for the high-speed and defence in depth finalists of the CAESAR competition for finding authenticated encryption ciphers. We eliminated the standard interfaces used during the competition. Through optimised interfaces between hardware and software, we were able to get both performance improvements as well as reduction in used programmable logic. The performance of our implementations is comparable to pure hardware implementations, but our implementations are 50% smaller. Compared to pure SW implementations we are 16 times faster. Comparing the different algorithms, we come to the conclusion that Colm allows the fastest implementation.
AB - In this work, we present five optimised implementations on a Xilinx-Zynq7200 SoC for the high-speed and defence in depth finalists of the CAESAR competition for finding authenticated encryption ciphers. We eliminated the standard interfaces used during the competition. Through optimised interfaces between hardware and software, we were able to get both performance improvements as well as reduction in used programmable logic. The performance of our implementations is comparable to pure hardware implementations, but our implementations are 50% smaller. Compared to pure SW implementations we are 16 times faster. Comparing the different algorithms, we come to the conclusion that Colm allows the fastest implementation.
UR - http://www.scopus.com/inward/record.url?scp=85068736744&partnerID=8YFLogxK
U2 - 10.1109/HST.2019.8740843
DO - 10.1109/HST.2019.8740843
M3 - Conference contribution
AN - SCOPUS:85068736744
T3 - Proceedings of the 2019 IEEE International Symposium on Hardware Oriented Security and Trust, HOST 2019
SP - 228
EP - 237
BT - Proceedings of the 2019 IEEE International Symposium on Hardware Oriented Security and Trust, HOST 2019
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2019 IEEE International Symposium on Hardware Oriented Security and Trust, HOST 2019
Y2 - 6 May 2019 through 10 May 2019
ER -