Using Graph Neural Networks for Timing Estimations of RTL Intermediate Representations

Accurate timing information of a digital design is available only after routing. Timing violations require corrective changes, even at the register-transfer level (RTL). Thus, timing feedback at RTL could guide micro-architecture search and reduce design iterations. However, this feedback is time-consuming, requiring synthesis and timing analysis runs. Related works have recognized timing estimations' value in the digital design flow. Most approaches use the pre-routing gate-level netlist as input, losing the RTL mapping. Others estimate either individual component delays or only global timing metrics from RTL designs. This paper uses graph neural networks (GNNs) to estimate a design's maximum arrival time (AT) by leveraging component delay and slew prediction. Our approach takes as input an RTL intermediate graph representation provided by an RTL generation tool and timing metrics collected from open-source synthesis tools. Experimental results show that the best architecture achieves a coefficient of determination R² of 0.82 and a maximum error of 3.79 ns for the AT prediction. The GNNs inference runtimes are three orders of magnitude faster than running RTL generation, synthesis, and timing analysis tools. Fast yet accurate estimations of ATs of an RTL could guide micro-architecture search at the early stages of the design.