TY - GEN
T1 - Transitioning spiking neural network simulators to heterogeneous hardware
AU - Nguyen, Quang Anh Pham
AU - Andelfinger, Philipp
AU - Cai, Wentong
AU - Knoll, Alois
N1 - Publisher Copyright:
© 2019 Copyright held by the owner/author(s). Publication rights licensed to ACM.
PY - 2019/5/29
Y1 - 2019/5/29
N2 - Spiking neural networks (SNN) are among the most computationally intensive types of simulation models, with node counts on the order of up to 1011. Currently, there is intensive research into hardware platforms suitable to support large-scale SNN simulations, whereas several of the most widely used simulators still rely purely on the execution on CPUs. Enabling the execution of these established simulators on heterogeneous hardware allows new studies to exploit the many-core hardware prevalent in modern supercomputing environments, while still being able to reproduce and compare with results from a vast body of existing literature. In this paper, we propose a transition approach for CPU-based SNN simulators to enable the execution on heterogeneous hardware (e.g., CPUs, GPUs, and FPGAs) with only limited modifications to an existing simulator code base, and without changes to model code. Our approach relies on manual porting of a small number of core simulator functionalities as found in common SNN simulators, whereas unmodified model code is analyzed and transformed automatically. We apply our approach to the well-known simulator NEST and make a version executable on heterogeneous hardware available to the community. Our measurements show that at full utilization, a single GPU achieves the performance of about 9 CPU cores.
AB - Spiking neural networks (SNN) are among the most computationally intensive types of simulation models, with node counts on the order of up to 1011. Currently, there is intensive research into hardware platforms suitable to support large-scale SNN simulations, whereas several of the most widely used simulators still rely purely on the execution on CPUs. Enabling the execution of these established simulators on heterogeneous hardware allows new studies to exploit the many-core hardware prevalent in modern supercomputing environments, while still being able to reproduce and compare with results from a vast body of existing literature. In this paper, we propose a transition approach for CPU-based SNN simulators to enable the execution on heterogeneous hardware (e.g., CPUs, GPUs, and FPGAs) with only limited modifications to an existing simulator code base, and without changes to model code. Our approach relies on manual porting of a small number of core simulator functionalities as found in common SNN simulators, whereas unmodified model code is analyzed and transformed automatically. We apply our approach to the well-known simulator NEST and make a version executable on heterogeneous hardware available to the community. Our measurements show that at full utilization, a single GPU achieves the performance of about 9 CPU cores.
UR - http://www.scopus.com/inward/record.url?scp=85067104095&partnerID=8YFLogxK
U2 - 10.1145/3316480.3322893
DO - 10.1145/3316480.3322893
M3 - Conference contribution
AN - SCOPUS:85067104095
T3 - SIGSIM-PADS 2019 - Proceedings of the 2019 ACM SIGSIM Conference on Principles of Advanced Discrete Simulation
SP - 115
EP - 126
BT - SIGSIM-PADS 2019 - Proceedings of the 2019 ACM SIGSIM Conference on Principles of Advanced Discrete Simulation
PB - Association for Computing Machinery, Inc
T2 - 2019 ACM SIGSIM Conference on Principles of Advanced Discrete Simulation, SIGSIM-PADS 2019
Y2 - 3 June 2019 through 5 June 2019
ER -