TY - GEN
T1 - Towards a Python-Based One Language Ecosystem for Embedded Systems Automation
AU - Han, Zhao
AU - Devarajegowda, Keerthikumara
AU - Werner, Michael
AU - Ecker, Wolfgang
N1 - Publisher Copyright:
© 2019 IEEE.
PY - 2019/10
Y1 - 2019/10
N2 - Design productivity remains a big problem in current embedded system development. Domain-Specific Languages (DSLs) are a promising measure to accelerate the development cycle. However, the inconsistent syntax in various DSLs, during system development and manual DSL development negatively impact any gained productivity. In this paper, we propose a metamodel-based framework for the generation of Python-embedded DSLs. A target metamodel abstracts models by defining elementary building blocks. With an additional configuration, our framework generates an expressive DSL which automates model construction and enables dataflow programming. By applying the proposed framework on different target meta-models, a 'One Language Ecosystem' is formed with the generated DSLs describing RTL, firmware and formal properties. As a proof of concept, a System on a Chip (SoC) consisting of RTL code and a firmware stack is generated, and formal properties are automated to verify the hardware components. To develop the RTL DSL, a time reduction by a factor-of-six is observed by using this generative approach. Furthermore, by comparing the DSL description to the generated target code, a code reduction by a factor-of-eight is given.
AB - Design productivity remains a big problem in current embedded system development. Domain-Specific Languages (DSLs) are a promising measure to accelerate the development cycle. However, the inconsistent syntax in various DSLs, during system development and manual DSL development negatively impact any gained productivity. In this paper, we propose a metamodel-based framework for the generation of Python-embedded DSLs. A target metamodel abstracts models by defining elementary building blocks. With an additional configuration, our framework generates an expressive DSL which automates model construction and enables dataflow programming. By applying the proposed framework on different target meta-models, a 'One Language Ecosystem' is formed with the generated DSLs describing RTL, firmware and formal properties. As a proof of concept, a System on a Chip (SoC) consisting of RTL code and a firmware stack is generated, and formal properties are automated to verify the hardware components. To develop the RTL DSL, a time reduction by a factor-of-six is observed by using this generative approach. Furthermore, by comparing the DSL description to the generated target code, a code reduction by a factor-of-eight is given.
KW - Design Automation
KW - Domain-Specific Language Generation
KW - Metamodeling
UR - http://www.scopus.com/inward/record.url?scp=85076031307&partnerID=8YFLogxK
U2 - 10.1109/NORCHIP.2019.8906949
DO - 10.1109/NORCHIP.2019.8906949
M3 - Conference contribution
AN - SCOPUS:85076031307
T3 - 2019 IEEE Nordic Circuits and Systems Conference, NORCAS 2019: NORCHIP and International Symposium of System-on-Chip, SoC 2019 - Proceedings
BT - 2019 IEEE Nordic Circuits and Systems Conference, NORCAS 2019
A2 - Nurmi, Jari
A2 - Ellervee, Peeter
A2 - Halonen, Kari
A2 - Roning, Juha
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 5th IEEE Nordic Circuits and Systems Conference, NORCAS 2019: NORCHIP and International Symposium of System-on-Chip, SoC 2019
Y2 - 29 October 2019 through 30 October 2019
ER -