Timing violations due to v_DD/V_SS bounce

Keyphrases

• Design Measures 50%
• Digital Circuits 50%
• IR Drop 100%
• On-chip Power Grid 50%
• Path Delay 100%
• Performance Implications 50%
• Power Grid Design 50%
• Power Supply Noise 50%
• Timing Violation 100%

Engineering

• Digital Circuits 50%
• Power Grid 100%
• Power Supply 50%
• Simulation Result 50%