The sizing rules method for CMOS and bipolar analog integrated circuit synthesis

Tobias Massier, Helmut Graeb, Ulf Schlichtmann

Publikation: Beitrag in FachzeitschriftArtikelBegutachtung

138 Zitate (Scopus)

Abstract

This paper presents the sizing rules method for basic building blocks in analog CMOS and bipolar circuit design. It consists of the development of a hierarchical library of transistorpair groups as basic building blocks for analog CMOS and bipolar circuits, the derivation of a hierarchical generic list of constraints that must be satisfied to guarantee the function and robustness of each block, and the development of a reliable automatic recognition procedure of building blocks in a circuit schematic. Sizing rules efficiently capture design knowledge on the technology-specific level of transistor-pair groups. This reduces the effort and improves the resulting quality for analog circuit synthesis. Results of applications like circuit sizing, design centering, response surface modeling, or analog placement show the benefits of the sizing rules method.

OriginalspracheEnglisch
Aufsatznummer4670074
Seiten (von - bis)2209-2222
Seitenumfang14
FachzeitschriftIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Jahrgang27
Ausgabenummer12
DOIs
PublikationsstatusVeröffentlicht - Dez. 2008

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