The optimal wire order for low power CMOS

Paul Zuber; Peter Gritzmann; Michael Ritter; Walter Stechele

doi:10.1007/11556930_69

The optimal wire order for low power CMOS

Paul Zuber, Peter Gritzmann, Michael Ritter, Walter Stechele

Technische Universität München

Publikation: Beitrag in Buch/Bericht/Konferenzband › Konferenzbeitrag › Begutachtung

2 Zitate (Scopus)

Abstract

If adjacent wires are brought into a simple specific order of their switching activities, the effect of power optimal wire spacing can be increased. In this paper we will present this order along with a prove of this observation. For this purpose, it is shown how to derive the new power optimal wire positions by solving a geometric program. Due to their simplicity in implementation, both principles reported substantially differ from previous approaches. We also quantify the power optimization potential for wires based on a representative circuit model, with promising results.

Originalsprache	Englisch
Titel	Integrated Circuit and System Design
Untertitel	Power and Timing Modeling, Optimization and Simulation - 15th International Workshop, PATMOS 2005, Proceedings
Herausgeber (Verlag)	Springer Verlag
Seiten	674-683
Seitenumfang	10
ISBN (Print)	3540290133, 9783540290131
DOIs	https://doi.org/10.1007/11556930_69
Publikationsstatus	Veröffentlicht - 2005
Veranstaltung	15th International Workshop on Integrated Circuit and System Design: Power and Timing Modeling, Optimization and Simulation, PATMOS 2005 - Leuven, Belgien Dauer: 20 Sept. 2005 → 23 Sept. 2005

Publikationsreihe

Name	Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Band	3728 LNCS
ISSN (Print)	0302-9743
ISSN (elektronisch)	1611-3349

Konferenz

Konferenz	15th International Workshop on Integrated Circuit and System Design: Power and Timing Modeling, Optimization and Simulation, PATMOS 2005
Land/Gebiet	Belgien
Ort	Leuven
Zeitraum	20/09/05 → 23/09/05

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10.1007/11556930_69

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Zuber, P., Gritzmann, P., Ritter, M., & Stechele, W. (2005). The optimal wire order for low power CMOS. in Integrated Circuit and System Design: Power and Timing Modeling, Optimization and Simulation - 15th International Workshop, PATMOS 2005, Proceedings (S. 674-683). (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); Band 3728 LNCS). Springer Verlag. https://doi.org/10.1007/11556930_69

Zuber, Paul ; Gritzmann, Peter ; Ritter, Michael et al. / The optimal wire order for low power CMOS. Integrated Circuit and System Design: Power and Timing Modeling, Optimization and Simulation - 15th International Workshop, PATMOS 2005, Proceedings. Springer Verlag, 2005. S. 674-683 (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)).

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abstract = "If adjacent wires are brought into a simple specific order of their switching activities, the effect of power optimal wire spacing can be increased. In this paper we will present this order along with a prove of this observation. For this purpose, it is shown how to derive the new power optimal wire positions by solving a geometric program. Due to their simplicity in implementation, both principles reported substantially differ from previous approaches. We also quantify the power optimization potential for wires based on a representative circuit model, with promising results.",

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Zuber, P, Gritzmann, P, Ritter, M & Stechele, W 2005, The optimal wire order for low power CMOS. in Integrated Circuit and System Design: Power and Timing Modeling, Optimization and Simulation - 15th International Workshop, PATMOS 2005, Proceedings. Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), Bd. 3728 LNCS, Springer Verlag, S. 674-683, 15th International Workshop on Integrated Circuit and System Design: Power and Timing Modeling, Optimization and Simulation, PATMOS 2005, Leuven, Belgien, 20/09/05. https://doi.org/10.1007/11556930_69

The optimal wire order for low power CMOS. / Zuber, Paul; Gritzmann, Peter; Ritter, Michael et al.
Integrated Circuit and System Design: Power and Timing Modeling, Optimization and Simulation - 15th International Workshop, PATMOS 2005, Proceedings. Springer Verlag, 2005. S. 674-683 (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); Band 3728 LNCS).

Publikation: Beitrag in Buch/Bericht/Konferenzband › Konferenzbeitrag › Begutachtung

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T1 - The optimal wire order for low power CMOS

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AU - Ritter, Michael

AU - Stechele, Walter

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AB - If adjacent wires are brought into a simple specific order of their switching activities, the effect of power optimal wire spacing can be increased. In this paper we will present this order along with a prove of this observation. For this purpose, it is shown how to derive the new power optimal wire positions by solving a geometric program. Due to their simplicity in implementation, both principles reported substantially differ from previous approaches. We also quantify the power optimization potential for wires based on a representative circuit model, with promising results.

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SN - 9783540290131

T3 - Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

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Zuber P, Gritzmann P, Ritter M, Stechele W. The optimal wire order for low power CMOS. in Integrated Circuit and System Design: Power and Timing Modeling, Optimization and Simulation - 15th International Workshop, PATMOS 2005, Proceedings. Springer Verlag. 2005. S. 674-683. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)). doi: 10.1007/11556930_69

The optimal wire order for low power CMOS

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