Tackling the MPSoC data locality challenge

Data access latencies and bandwidth bottlenecks frequently represent major limiting factors for the computational effectiveness of multi- and many-core processor architectures. This chapter deals with two conceptually complementary approaches to ensure that the data to be processed and the processing entities remain spatially confined, even under fluctuating workload and application compositions: region-based cache coherence (RBCC) and near-memory acceleration (NMA). In addition, so-called near-cache accelerators (NCA) are proposed and investigated. As the cache hierarchy is often bypassed when integrating in- or near-memory solutions, they need to be properly synchronized with the rest of the system, i.e., maintaining coherence and consistency between normal cores and NMAs. The efficiency and scalability of cache coherence plays an important role for tile-based MPSoCs. Both RBCC and NCA/NMA contribute to tackling the MPSoC data locality challenge for native as well as hybrid forms of distributed shared memory and shared memory models and architectures.