Subtype concept of VHDL for synthesis constraints

In this paper, we propose to exploit the VHDL subtype concept for formulating ranges for design constraints which could be used as input for synthesis tools. The proposed method relies on interpreting the range of a VHDL constant's type as a range specification for a design constraint. Presynthesis simulation is done with an estimated value inside the specified range. Postsynthesis simulation in order to check functionality as well as consistency with design constraints is performed by using the actual values resulting from synthesis.