Statistical characterization of hold time violations in 130nm CMOS technology

Gustavo Neuberger; Fernanda Kastensmidt; Ricardo Reis; Gilson Wirth; Ralf Brederlow; Christian Pacha

doi:10.1109/ESSCIR.2006.307544

Statistical characterization of hold time violations in 130nm CMOS technology

Gustavo Neuberger, Fernanda Kastensmidt, Ricardo Reis, Gilson Wirth, Ralf Brederlow, Christian Pacha

Publikation: Beitrag in Buch/Bericht/Konferenzband › Konferenzbeitrag › Begutachtung

5 Zitate (Scopus)

Abstract

Statistical process variations are a critical issue for circuit design strategies to ensure high yield in sub-100nm technologies. In this work we present an on-chip measurement technique to characterize hold time violations of flip-flops in short logic paths, which are generated by clock-edge uncertainties in synchronous designs. Using a precise programmable clock-to-data skew generation circuit, a measurement resolution of ~∼1ps is achieved to emulate race conditions. Statistical variations of hold time violations are measured in a 130nm low-power CMOS technology for various register-to-register configurations and show 3a die-to-die standard deviations of up to 15%.

Originalsprache	Englisch
Titel	ESSCIRC 2006 - Proceedings of the 32nd European Solid-State Circuits Conference
Seiten	114-117
Seitenumfang	4
DOIs	https://doi.org/10.1109/ESSCIR.2006.307544
Publikationsstatus	Veröffentlicht - 2006
Extern publiziert	Ja
Veranstaltung	ESSCIRC 2006 - 32nd European Solid-State Circuits Conference - Montreux, Schweiz Dauer: 19 Sept. 2006 → 21 Sept. 2006

Publikationsreihe

Name	ESSCIRC 2006 - Proceedings of the 32nd European Solid-State Circuits Conference

Konferenz

Konferenz	ESSCIRC 2006 - 32nd European Solid-State Circuits Conference
Land/Gebiet	Schweiz
Ort	Montreux
Zeitraum	19/09/06 → 21/09/06

Zugriff auf Dokument

10.1109/ESSCIR.2006.307544

Andere Dateien und Links

Verknüpfung zur Publikation in Scopus

Dieses zitieren

Neuberger, G., Kastensmidt, F., Reis, R., Wirth, G., Brederlow, R., & Pacha, C. (2006). Statistical characterization of hold time violations in 130nm CMOS technology. in ESSCIRC 2006 - Proceedings of the 32nd European Solid-State Circuits Conference (S. 114-117). Artikel 4099717 (ESSCIRC 2006 - Proceedings of the 32nd European Solid-State Circuits Conference). https://doi.org/10.1109/ESSCIR.2006.307544

@inproceedings{a1df29797b6d49f287a6d38e56ca6433,

title = "Statistical characterization of hold time violations in 130nm CMOS technology",

abstract = "Statistical process variations are a critical issue for circuit design strategies to ensure high yield in sub-100nm technologies. In this work we present an on-chip measurement technique to characterize hold time violations of flip-flops in short logic paths, which are generated by clock-edge uncertainties in synchronous designs. Using a precise programmable clock-to-data skew generation circuit, a measurement resolution of ~∼1ps is achieved to emulate race conditions. Statistical variations of hold time violations are measured in a 130nm low-power CMOS technology for various register-to-register configurations and show 3a die-to-die standard deviations of up to 15%.",

author = "Gustavo Neuberger and Fernanda Kastensmidt and Ricardo Reis and Gilson Wirth and Ralf Brederlow and Christian Pacha",

year = "2006",

doi = "10.1109/ESSCIR.2006.307544",

language = "English",

isbn = "1424403022",

series = "ESSCIRC 2006 - Proceedings of the 32nd European Solid-State Circuits Conference",

pages = "114--117",

booktitle = "ESSCIRC 2006 - Proceedings of the 32nd European Solid-State Circuits Conference",

note = "ESSCIRC 2006 - 32nd European Solid-State Circuits Conference ; Conference date: 19-09-2006 Through 21-09-2006",

}

Neuberger, G, Kastensmidt, F, Reis, R, Wirth, G, Brederlow, R & Pacha, C 2006, Statistical characterization of hold time violations in 130nm CMOS technology. in ESSCIRC 2006 - Proceedings of the 32nd European Solid-State Circuits Conference., 4099717, ESSCIRC 2006 - Proceedings of the 32nd European Solid-State Circuits Conference, S. 114-117, ESSCIRC 2006 - 32nd European Solid-State Circuits Conference, Montreux, Schweiz, 19/09/06. https://doi.org/10.1109/ESSCIR.2006.307544

Statistical characterization of hold time violations in 130nm CMOS technology. / Neuberger, Gustavo; Kastensmidt, Fernanda; Reis, Ricardo et al.
ESSCIRC 2006 - Proceedings of the 32nd European Solid-State Circuits Conference. 2006. S. 114-117 4099717 (ESSCIRC 2006 - Proceedings of the 32nd European Solid-State Circuits Conference).

Publikation: Beitrag in Buch/Bericht/Konferenzband › Konferenzbeitrag › Begutachtung

TY - GEN

T1 - Statistical characterization of hold time violations in 130nm CMOS technology

AU - Neuberger, Gustavo

AU - Kastensmidt, Fernanda

AU - Reis, Ricardo

AU - Wirth, Gilson

AU - Brederlow, Ralf

AU - Pacha, Christian

PY - 2006

Y1 - 2006

N2 - Statistical process variations are a critical issue for circuit design strategies to ensure high yield in sub-100nm technologies. In this work we present an on-chip measurement technique to characterize hold time violations of flip-flops in short logic paths, which are generated by clock-edge uncertainties in synchronous designs. Using a precise programmable clock-to-data skew generation circuit, a measurement resolution of ~∼1ps is achieved to emulate race conditions. Statistical variations of hold time violations are measured in a 130nm low-power CMOS technology for various register-to-register configurations and show 3a die-to-die standard deviations of up to 15%.

AB - Statistical process variations are a critical issue for circuit design strategies to ensure high yield in sub-100nm technologies. In this work we present an on-chip measurement technique to characterize hold time violations of flip-flops in short logic paths, which are generated by clock-edge uncertainties in synchronous designs. Using a precise programmable clock-to-data skew generation circuit, a measurement resolution of ~∼1ps is achieved to emulate race conditions. Statistical variations of hold time violations are measured in a 130nm low-power CMOS technology for various register-to-register configurations and show 3a die-to-die standard deviations of up to 15%.

UR - http://www.scopus.com/inward/record.url?scp=70949087833&partnerID=8YFLogxK

U2 - 10.1109/ESSCIR.2006.307544

DO - 10.1109/ESSCIR.2006.307544

M3 - Conference contribution

AN - SCOPUS:70949087833

SN - 1424403022

SN - 9781424403028

T3 - ESSCIRC 2006 - Proceedings of the 32nd European Solid-State Circuits Conference

SP - 114

EP - 117

BT - ESSCIRC 2006 - Proceedings of the 32nd European Solid-State Circuits Conference

T2 - ESSCIRC 2006 - 32nd European Solid-State Circuits Conference

Y2 - 19 September 2006 through 21 September 2006

ER -

Neuberger G, Kastensmidt F, Reis R, Wirth G, Brederlow R, Pacha C. Statistical characterization of hold time violations in 130nm CMOS technology. in ESSCIRC 2006 - Proceedings of the 32nd European Solid-State Circuits Conference. 2006. S. 114-117. 4099717. (ESSCIRC 2006 - Proceedings of the 32nd European Solid-State Circuits Conference). doi: 10.1109/ESSCIR.2006.307544

Statistical characterization of hold time violations in 130nm CMOS technology

Abstract

Publikationsreihe

Konferenz

Zugriff auf Dokument

Andere Dateien und Links

Fingerprint

Dieses zitieren