TY - GEN
T1 - Specification language for transaction level assertions
AU - Ecker, Wolfgang
AU - Esen, Volkan
AU - Steininger, Thomas
AU - Velten, Michael
AU - Hull, Michael
PY - 2006
Y1 - 2006
N2 - Transaction level (TL) modeling is the basis of the so called Electronic System Level that allows development of systems on chip at a quicker pace than with classical RTL approaches. Starting from the specification phase of the product development cycle, TL modeling enables easy architecture exploration and early software co-development. In contrast to RTL, TL models (TLM) are more abstract and do not contain micro-architectural details for instance; the design focus is on high-level control and data flow. Since TLMs are essential at the decision process in early system development and as they can serve as golden reference models for later RTL regression, it is imperative to ensure that they implement the specification correctly. Assertion Based Verification (ABV) has given a good return of investment in RTL verification, decreasing debug time while preserving the design intent. Leveraging these benefits on the transaction level for the verification of TLMs requires the adaptation of current ABV approaches to the specific characteristics of these abstract models. In this paper we present an assertion specification language, based on formal definitions, that allows the specification of transaction level properties and their execution in simulation. We derive the language from known ABV languages and extend these by the required TL functionality, and explain how simulation traces of finite length can be checked against properties.
AB - Transaction level (TL) modeling is the basis of the so called Electronic System Level that allows development of systems on chip at a quicker pace than with classical RTL approaches. Starting from the specification phase of the product development cycle, TL modeling enables easy architecture exploration and early software co-development. In contrast to RTL, TL models (TLM) are more abstract and do not contain micro-architectural details for instance; the design focus is on high-level control and data flow. Since TLMs are essential at the decision process in early system development and as they can serve as golden reference models for later RTL regression, it is imperative to ensure that they implement the specification correctly. Assertion Based Verification (ABV) has given a good return of investment in RTL verification, decreasing debug time while preserving the design intent. Leveraging these benefits on the transaction level for the verification of TLMs requires the adaptation of current ABV approaches to the specific characteristics of these abstract models. In this paper we present an assertion specification language, based on formal definitions, that allows the specification of transaction level properties and their execution in simulation. We derive the language from known ABV languages and extend these by the required TL functionality, and explain how simulation traces of finite length can be checked against properties.
UR - http://www.scopus.com/inward/record.url?scp=46249112710&partnerID=8YFLogxK
U2 - 10.1109/HLDVT.2006.319967
DO - 10.1109/HLDVT.2006.319967
M3 - Conference contribution
AN - SCOPUS:46249112710
SN - 142440679X
SN - 9781424406791
T3 - Proceedings - IEEE International High-Level Design Validation and Test Workshop, HLDVT
SP - 77
EP - 84
BT - Proceedings - 11th Annual IEEE International High-Level Design Validation and Test Workshop, HLDVT'06
T2 - 11th Annual IEEE International High-Level Design Validation and Test Workshop, HLDVT'06
Y2 - 8 November 2006 through 10 November 2006
ER -