SOC design automation with ML - It's time for research

The AI-hype started a few years ago, with advances in object recognition. Soon the EDA research community made proposals on applying AI in EDA and all major players announced new AI-based tools at DAC 2018. Unfortunately, few new AI-based EDA-tools made it to productive use today. This talk analyses general challenges of AI in EDA, outlines promising use cases, and motivates more AI research in EDA: More HI (=Human Intelligence) is needed to make AI successful in EDA. Motivation: For a long time, hardware design resides in an area between hell of complexity and hell of physics. Continuously decreasing feature size enables to put more and more transistors on a square millimeter silicon. This offers to make continuously new applications at a reasonable form factor. However, the functionality of the application must be designed first and the deep submicron effects must be considered properly. EDA tools help to automate design, but face challenges keeping up with the continuously increasing productivity demand. Therefore, the design teams have increased in size to step up the design of the chips. So, any further innovation is welcome. The rediscovery of AI in general and ML in particular created visions of learning from designers and automatically creating automation from these learnings. To give an example, Google describes in [1] how to accelerate Chip Placement from weeks to hours. Problem statement: There are three main challenges to foster the use of AI in EDA. First, it is not straightforward to come up with a business model for AI in EDA. The open question is, which amount of improvement users do expect without paying higher license fees. Also, how much would they be willing to pay for a tool which improves the overall efficiency and reduces the number of licenses for other tools in use. Second, AI requires large amount of data for learning. A common infrastructural setup cost in gathering the technology specific design data is high due to long tool runs and additional license cost at the user end.. For instance, setting the right tool switches for optimum compile and synthesis is a good application area for AI in EDA. Reports about optimizing the “gcc” compiler and “Vivado” show the potential of this technology. However there is no solution for R2G tools available. Third, AI methods cannot be easily integrated into EDA solutions. E.g. Infineon developed with a partner an approach to optimize the pattern of a regression run. Efficiency improvements of over 60% were reached. However, it works with pre-generated pattern only, since there was no way to integrate the approach in a UVM simulator. Approach: In the context of design automation, Infineon is using AI for cost estimation and optimization in early design phases [2]. Here, AI shows its strength since it is able to handle a quite uncorrelated set of data such as SW memory size and SW execution time, and the dependency on hardware structure, implementation style and optimization level. This is enabled by the Infineon MDA code generation framework to automatically make a wide variety of consistent HW- and SW implementations to train the AI [3]. Furthermore, Infineon starts to make use of OpenROAD [4] to collect ASIC relevant data and clearly welcomes all further research that goes into this framework. Since this only partially solves the challenge of a sufficient amount of training data, Infineon sees research demand in pre-processing ASIC data and/or approaches to use pre-learned networks. Both are needed to apply AI techniques in several technology domains and variants releasing from the burden of exhaustively retraining the AI.