Saving potentials of adiab. logic on system level: A CORDIC-based adiabatic DCT

The energy consumption of digital systems can be greatly reduced by applying Adiabatic Logic (AL). Making best use of AL requires a dedicated system design regarding the inherent characteristics of AL. In this paper we investigate the CORDIC architecture, that can be used for various signal processing algorithms and is preeminently suitable for AL. For fast functional testing, we propose a methodology to describe AL in VHDL. An adiabatic CORDIC-based DCT is used as a test vehicle to demonstrate on system level the applicability of AL for ultra-low-power digital signal processing. We present an estimation method for the energy consumption and therewith compare a variety of static CMOS implementations of the DCT to our adiabatic DCT. The estimation results are verified by simulating the whole system in a 130nm CMOS technology for various supply voltages. Even at a low supply voltage of 0.8V the adiabatic DCT's energy consumption is less than 15% compared to the static CMOS implementation.